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[PULL 35/38] target/riscv: Allow enabling the Hypervisor extension
From: |
Palmer Dabbelt |
Subject: |
[PULL 35/38] target/riscv: Allow enabling the Hypervisor extension |
Date: |
Mon, 2 Mar 2020 16:48:45 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 5 +++++
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b27066f6a7..c47d10b739 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
+ if (cpu->cfg.ext_h) {
+ target_misa |= RVH;
+ }
set_misa(env, RVXLEN | target_misa);
}
@@ -488,6 +491,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ /* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6f9c29322a..d52f209361 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -258,6 +258,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 23/38] target/riscv: Add hfence instructions, (continued)
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status, Palmer Dabbelt, 2020/03/02
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02
- [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops, Palmer Dabbelt, 2020/03/02
- [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Palmer Dabbelt, 2020/03/02
- [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension,
Palmer Dabbelt <=
- [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation, Palmer Dabbelt, 2020/03/02
- [PULL 36/38] riscv: virt: Allow PCI address 0, Palmer Dabbelt, 2020/03/02
- [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode, Palmer Dabbelt, 2020/03/02
- [PULL 32/38] target/riscv: Set htval and mtval2 on execptions, Palmer Dabbelt, 2020/03/02
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Peter Maydell, 2020/03/03