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[PULL 36/38] riscv: virt: Allow PCI address 0
From: |
Palmer Dabbelt |
Subject: |
[PULL 36/38] riscv: virt: Allow PCI address 0 |
Date: |
Mon, 2 Mar 2020 16:48:46 -0800 |
From: Bin Meng <address@hidden>
When testing e1000 with the virt machine, e1000's I/O space cannot
be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
written with address 0 plus I/O enable bit, but QEMU's "info pci"
shows that:
Bus 0, device 1, function 0:
Ethernet controller: PCI device 8086:100e
...
BAR1: I/O at 0xffffffffffffffff [0x003e].
...
It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f9e1e5176..5d175d5c9e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -641,6 +641,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc,
void *data)
mc->init = riscv_virt_board_init;
mc->max_cpus = 8;
mc->default_cpu_type = VIRT_CPU;
+ mc->pci_allow_0_address = true;
}
static const TypeInfo riscv_virt_machine_typeinfo = {
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 24/38] target/riscv: Remove the hret instruction, (continued)
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status, Palmer Dabbelt, 2020/03/02
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02
- [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops, Palmer Dabbelt, 2020/03/02
- [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Palmer Dabbelt, 2020/03/02
- [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation, Palmer Dabbelt, 2020/03/02
- [PULL 36/38] riscv: virt: Allow PCI address 0,
Palmer Dabbelt <=
- [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode, Palmer Dabbelt, 2020/03/02
- [PULL 32/38] target/riscv: Set htval and mtval2 on execptions, Palmer Dabbelt, 2020/03/02
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Peter Maydell, 2020/03/03