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[PATCH v5 45/60] target/riscv: vector wideing integer reduction instruct
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions |
Date: |
Thu, 12 Mar 2020 22:58:45 +0800 |
Signed-off-by: LIU Zhiwei <address@hidden>
---
target/riscv/helper.h | 7 +++++++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++++
target/riscv/vector_helper.c | 11 +++++++++++
4 files changed, 24 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index cc1eb55404..76435f90a9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1054,3 +1054,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2419ef97e7..e6a354c134 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -531,6 +531,8 @@ vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
+vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
+vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 3f6951abd5..195c460cb8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2040,3 +2040,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
GEN_OPIVV_TRANS(vredand_vs, reduction_check)
GEN_OPIVV_TRANS(vredor_vs, reduction_check)
GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
+
+/* Vector Widening Integer Reduction Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 789be79b5a..f2ded5adc6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4138,3 +4138,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1,
DO_XOR, clearb)
GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+
+/* Vector Widening Integer Reduction Instructions */
+/* signed sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+
+/* Unsigned sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
--
2.23.0
- Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructions, (continued)
[PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 43/60] target/riscv: narrowing floating-point/integer type-convert instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 44/60] target/riscv: vector single-width integer reduction instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions,
LIU Zhiwei <=
[PATCH v5 46/60] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 48/60] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 49/60] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/12
[PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/12