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Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructio
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions |
Date: |
Sat, 14 Mar 2020 23:48:41 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/14/20 11:13 PM, LIU Zhiwei wrote:
>> SEW == MO_8 should raise illegal instruction exception.
> I agree. But I didn't find a reference in Section 17.3 both in v0.7.1 and
> v0.8.
>
> Perhaps I should refer
>
> "If the current SEW does not correspond to a supported IEEE floating-point
> type, an illegal instruction exception is raised."(Section 14)
Yes, that's the rule I was thinking of.
>> Missing nan-boxing for SEW==MO_64 && FLEN==32 (!RVD). Which I think should
>> be
>> done here inline, so that the uint64_t passed to the helper is always
>> correct.
> I think all float registers have been NAN-boxed in QEMU target/riscv.
>
> As float registers are always 64bits. If FLEN is 32, a float register has
> been NAN-boxed in FLW or VFMV.F.S
>
> Should I NAN-boxed the float register explicitly here ?
Hmm, I see what you mean -- RVF is supposed to have already boxed all of the
values. Except that it doesn't at the moment. I remember now that we were
talking about this some months ago; I thought it had been taken care of, but
hasn't.
I think we should explicitly do it here, with a comment.
r~
[PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/15
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/24
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/24