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Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructio
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions |
Date: |
Tue, 17 Mar 2020 08:11:29 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/16/20 11:01 PM, LIU Zhiwei wrote:
> Two questions here. I don't find the answer in the specification.
>
> 1. Should I check RVF if the instruction uses float register, such as all
> float point instructions and some other instructions?
I would think so, but even the 0.8 spec isn't clear.
> 2. Should I check mstatus_fs if the instruction uses float registers, or just
> for instructions that write float point register?
Definitely, just like the regular fp instructions.
This trap is how the kernel implements lazy fp context switching, so if you
allow access to fp when disabled you may be accessing values from a different
process.
r~
- Re: [PATCH v5 54/60] target/riscv: integer extract instruction, (continued)
[PATCH v5 55/60] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/03/12
[PATCH v5 56/60] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/15
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/16
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/24
- Re: [PATCH v5 57/60] target/riscv: vector slide instructions, Richard Henderson, 2020/03/24
[PATCH v5 58/60] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/12