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From: | Richard Henderson |
Subject: | Re: [PATCH v6 09/61] target/riscv: add vector amo operations |
Date: | Fri, 27 Mar 2020 16:44:52 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote: > Vector AMOs operate as if aq and rl bits were zero on each element > with regard to ordering relative to other instructions in the same hart. > Vector AMOs provide no ordering guarantee between element operations > in the same vector AMO instruction > > Signed-off-by: LIU Zhiwei <address@hidden> > --- > target/riscv/helper.h | 29 +++++ > target/riscv/insn32-64.decode | 11 ++ > target/riscv/insn32.decode | 13 +++ > target/riscv/insn_trans/trans_rvv.inc.c | 134 ++++++++++++++++++++++ > target/riscv/internals.h | 1 + > target/riscv/vector_helper.c | 143 ++++++++++++++++++++++++ > 6 files changed, 331 insertions(+) Reviewed-by: Richard Henderson <address@hidden> r~
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