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Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and s
From: |
Richard Henderson |
Subject: |
Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract |
Date: |
Fri, 27 Mar 2020 16:54:25 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> + if (a->vm && s->vl_eq_vlmax) {
> + gvec_fn(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
> + MAXSZ(s), MAXSZ(s));
Indentation is off here.
> +static inline bool
> +do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
> + gen_helper_opivx *fn)
> +{
> + if (!opivx_check(s, a)) {
> + return false;
> + }
> +
> + if (a->vm && s->vl_eq_vlmax) {
> + TCGv_i64 src1 = tcg_temp_new_i64();
> + TCGv tmp = tcg_temp_new();
> +
> + gen_get_gpr(tmp, a->rs1);
> + tcg_gen_ext_tl_i64(src1, tmp);
> + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
> + src1, MAXSZ(s), MAXSZ(s));
> +
> + tcg_temp_free_i64(src1);
> + tcg_temp_free(tmp);
> + return true;
> + } else {
> + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + }
> + return true;
> +}
This final return is unreachable, and I'm sure some static analyzer (e.g.
Coverity) will complain.
Since the if-then has a return, we can drop the else like so:
if (a->vm && s->vl_eq_vlmax) {
...
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [PATCH v6 05/61] target/riscv: add an internals.h header, (continued)
- [PATCH v6 06/61] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 07/61] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 08/61] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/17
- [PATCH v6 09/61] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/17
- [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/17
- [PATCH v6 11/61] target/riscv: vector widening integer add and subtract, LIU Zhiwei, 2020/03/17
- [PATCH v6 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 13/61] target/riscv: vector bitwise logical instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 14/61] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/17