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[RFC v2 75/76] target/riscv: gdb: support vector registers for rv64
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From: |
frank . chang |
|
Subject: |
[RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 |
|
Date: |
Wed, 22 Jul 2020 17:16:38 +0800 |
From: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
configure | 2 +-
gdb-xml/riscv-64bit-csr.xml | 7 ++++
gdb-xml/riscv-64bit-vector-128b.xml | 59 +++++++++++++++++++++++++++
gdb-xml/riscv-64bit-vector-256b.xml | 59 +++++++++++++++++++++++++++
gdb-xml/riscv-64bit-vector-512b.xml | 59 +++++++++++++++++++++++++++
target/riscv/gdbstub.c | 62 ++++++++++++++++++++++++++++-
6 files changed, 245 insertions(+), 3 deletions(-)
create mode 100644 gdb-xml/riscv-64bit-vector-128b.xml
create mode 100644 gdb-xml/riscv-64bit-vector-256b.xml
create mode 100644 gdb-xml/riscv-64bit-vector-512b.xml
diff --git a/configure b/configure
index ee6c3c6792..8d69013a97 100755
--- a/configure
+++ b/configure
@@ -8228,7 +8228,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-64bit-csr.xml riscv-64bit-virtual.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml
riscv-64bit-vector-512b.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;;
rx)
TARGET_ARCH=rx
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
index 9039456293..28a7c9a9f3 100644
--- a/gdb-xml/riscv-64bit-csr.xml
+++ b/gdb-xml/riscv-64bit-csr.xml
@@ -248,4 +248,11 @@
<reg name="mucounteren" bitsize="64"/>
<reg name="mscounteren" bitsize="64"/>
<reg name="mhcounteren" bitsize="64"/>
+ <reg name="vstart" bitsize="64"/>
+ <reg name="vxsat" bitsize="64"/>
+ <reg name="vxrm" bitsize="64"/>
+ <reg name="vcsr" bitsize="64"/>
+ <reg name="vl" bitsize="64"/>
+ <reg name="vtype" bitsize="64"/>
+ <reg name="vlenb" bitsize="64"/>
</feature>
diff --git a/gdb-xml/riscv-64bit-vector-128b.xml
b/gdb-xml/riscv-64bit-vector-128b.xml
new file mode 100644
index 0000000000..f6150968b3
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-128b.xml
@@ -0,0 +1,59 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.vector">
+<vector id="bytes" type="uint8" count="16"/>
+<vector id="shorts" type="uint16" count="8"/>
+<vector id="words" type="uint32" count="4"/>
+<vector id="longs" type="uint64" count="2"/>
+<vector id="quads" type="uint128" count="1"/>
+ <union id="riscv_vector">
+ <field name="b" type="bytes"/>
+ <field name="s" type="shorts"/>
+ <field name="w" type="words"/>
+ <field name="l" type="longs"/>
+ <field name="q" type="quads"/>
+ </union>
+
+ <reg name="v0" bitsize="128" save-restore="no" type="riscv_vector"
group="vector" regnum="69"/>
+ <reg name="v1" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v2" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v3" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v4" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v5" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v6" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v7" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v8" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v9" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v10" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v11" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v12" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v13" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v14" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v15" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v16" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v17" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v18" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v19" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v20" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v21" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v22" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v23" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v24" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v25" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v26" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v27" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v28" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v29" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v30" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v31" bitsize="128" save-restore="no" type="riscv_vector"
group="vector"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-vector-256b.xml
b/gdb-xml/riscv-64bit-vector-256b.xml
new file mode 100644
index 0000000000..6183846a35
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-256b.xml
@@ -0,0 +1,59 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.vector">
+<vector id="bytes" type="uint8" count="32"/>
+<vector id="shorts" type="uint16" count="16"/>
+<vector id="words" type="uint32" count="8"/>
+<vector id="longs" type="uint64" count="4"/>
+<vector id="quads" type="uint128" count="2"/>
+ <union id="riscv_vector">
+ <field name="b" type="bytes"/>
+ <field name="s" type="shorts"/>
+ <field name="w" type="words"/>
+ <field name="l" type="longs"/>
+ <field name="q" type="quads"/>
+ </union>
+
+ <reg name="v0" bitsize="256" save-restore="no" type="riscv_vector"
group="vector" regnum="69"/>
+ <reg name="v1" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v2" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v3" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v4" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v5" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v6" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v7" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v8" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v9" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v10" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v11" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v12" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v13" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v14" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v15" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v16" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v17" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v18" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v19" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v20" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v21" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v22" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v23" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v24" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v25" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v26" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v27" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v28" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v29" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v30" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v31" bitsize="256" save-restore="no" type="riscv_vector"
group="vector"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-vector-512b.xml
b/gdb-xml/riscv-64bit-vector-512b.xml
new file mode 100644
index 0000000000..78bb147cdf
--- /dev/null
+++ b/gdb-xml/riscv-64bit-vector-512b.xml
@@ -0,0 +1,59 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.vector">
+<vector id="bytes" type="uint8" count="64"/>
+<vector id="shorts" type="uint16" count="32"/>
+<vector id="words" type="uint32" count="16"/>
+<vector id="longs" type="uint64" count="8"/>
+<vector id="quads" type="uint128" count="4"/>
+ <union id="riscv_vector">
+ <field name="b" type="bytes"/>
+ <field name="s" type="shorts"/>
+ <field name="w" type="words"/>
+ <field name="l" type="longs"/>
+ <field name="q" type="quads"/>
+ </union>
+
+ <reg name="v0" bitsize="512" save-restore="no" type="riscv_vector"
group="vector" regnum="69"/>
+ <reg name="v1" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v2" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v3" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v4" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v5" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v6" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v7" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v8" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v9" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v10" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v11" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v12" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v13" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v14" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v15" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v16" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v17" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v18" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v19" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v20" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v21" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v22" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v23" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v24" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v25" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v26" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v27" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v28" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v29" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v30" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+ <reg name="v31" bitsize="512" save-restore="no" type="riscv_vector"
group="vector"/>
+</feature>
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f7c5212e27..1681f883e4 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -268,6 +268,13 @@ static int csr_register_map[] = {
CSR_MUCOUNTEREN,
CSR_MSCOUNTEREN,
CSR_MHCOUNTEREN,
+ CSR_VSTART,
+ CSR_VXSAT,
+ CSR_VXRM,
+ CSR_VCSR,
+ CSR_VL,
+ CSR_VTYPE,
+ CSR_VLENB,
};
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
@@ -351,6 +358,34 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
return 0;
}
+static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ int cnt = 0;
+ for (i = 0; i < vlenb; i += 8) {
+ cnt += gdb_get_reg64(buf,
+ env->vreg[(n * vlenb + i) / 8]);
+ }
+ return cnt;
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ for (i = 0; i < vlenb; i += 8) {
+ env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
+ }
+ return vlenb;
+ }
+ return 0;
+}
+
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < ARRAY_SIZE(csr_register_map)) {
@@ -416,15 +451,38 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
+ if (env->misa & RVV) {
+ /* TODO: support vlen other than 128, 256, 512 bits. */
+ const char *vector_xml_name = NULL;
+ switch (cpu->cfg.vlen) {
+ case 128:
+ vector_xml_name = "riscv-64bit-vector-128b.xml";
+ break;
+ case 256:
+ vector_xml_name = "riscv-64bit-vector-256b.xml";
+ break;
+ case 512:
+ vector_xml_name = "riscv-64bit-vector-512b.xml";
+ break;
+ default:
+ vector_xml_name = NULL;
+ break;
+ }
+ if (vector_xml_name) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+ riscv_gdb_set_vector,
+ 32, vector_xml_name, 0);
+ }
+ }
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- 241, "riscv-32bit-csr.xml", 0);
+ 248, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- 241, "riscv-64bit-csr.xml", 0);
+ 248, "riscv-64bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
--
2.17.1
- Re: [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction, (continued)
- [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/22
- [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/22
- [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/22
- [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 73/76] fpu: fix float16 nan check, frank . chang, 2020/07/22
- [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/07/22
- [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64,
frank . chang <=
- [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/07/22