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[RFC v2 76/76] target/riscv: gdb: support vector registers for rv32
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From: |
frank . chang |
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Subject: |
[RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 |
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Date: |
Wed, 22 Jul 2020 17:16:39 +0800 |
From: Greentime Hu <greentime.hu@sifive.com>
This patch adds vector support for rv32 gdb. It allows gdb client to access
vector registers correctly.
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 8d69013a97..dbe3c4e4c5 100755
--- a/configure
+++ b/configure
@@ -8222,7 +8222,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-32bit-csr.xml riscv-32bit-virtual.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml
riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml
riscv-64bit-vector-512b.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
;;
riscv64)
TARGET_BASE_ARCH=riscv
--
2.17.1
- [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions, (continued)
- [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/22
- [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions, frank . chang, 2020/07/22
- [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/22
- [RFC v2 73/76] fpu: fix float16 nan check, frank . chang, 2020/07/22
- [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/07/22
- [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/07/22
- [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32,
frank . chang <=