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Re: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point re


From: Richard Henderson
Subject: Re: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction
Date: Fri, 31 Jul 2020 09:45:45 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
>  # Vector ordered and unordered reduction sum
> -vfredsum_vs     0000-1 . ..... ..... 001 ..... 1010111 @r_vm
> +vfredsum_vs     000001 . ..... ..... 001 ..... 1010111 @r_vm
> +vfredosum_vs    000011 . ..... ..... 001 ..... 1010111 @r_vm

"The vfredosum instruction is a valid implementation of the vfredsum 
instruction."

Which is exactly what we're doing here.

Why should we treat them differently?  There is no parallelism that we can
exploit in tcg, unlike in hardware.


r~



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