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[RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions
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From: |
frank . chang |
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Subject: |
[RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions |
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Date: |
Wed, 22 Jul 2020 17:16:20 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
target/riscv/vector_helper.c | 7 +++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 378af8344d..5004707b87 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3023,7 +3023,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fa2459d941..bb426e224c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4738,6 +4738,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4747,8 +4748,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
} \
}
--
2.17.1
- [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions, (continued)
- [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions, frank . chang, 2020/07/22
- [RFC v2 52/76] fpu: implement full set compare for fp16, frank . chang, 2020/07/22
- [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/22
- [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions, frank . chang, 2020/07/22
- [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions, frank . chang, 2020/07/22
- [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions, frank . chang, 2020/07/22
- [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions,
frank . chang <=
- [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/22
- [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/22
- [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions, frank . chang, 2020/07/22
- [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions, frank . chang, 2020/07/22
- [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction, frank . chang, 2020/07/22