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[PATCH 5/6] target/riscv: fix checks in hmode/hmode32
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From: |
Weiwei Li |
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Subject: |
[PATCH 5/6] target/riscv: fix checks in hmode/hmode32 |
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Date: |
Sun, 10 Jul 2022 16:23:59 +0800 |
- It seems that there is no explicitly description about whether
the Hypervisor CSRs requires S extension
- Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/csr.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0d8e98b7a9..975007f1ac 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
static RISCVException hmode(CPURISCVState *env, int csrno)
{
- if (riscv_has_ext(env, RVS) &&
- riscv_has_ext(env, RVH)) {
+ if (riscv_has_ext(env, RVH)) {
/* Hypervisor extension is supported */
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
@@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (riscv_cpu_mxl(env) != MXL_RV32) {
- if (!riscv_cpu_virt_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- } else {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
+ return RISCV_EXCP_ILLEGAL_INST;
}
return hmode(env, csrno);
--
2.17.1
- [PATCH 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/10
- [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/10
- [PATCH 5/6] target/riscv: fix checks in hmode/hmode32,
Weiwei Li <=
- [PATCH 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/10
- [PATCH 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/10
- [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/10
- [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/10