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[PATCH 2/6] target/riscv: H extension depends on I extension
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From: |
Weiwei Li |
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Subject: |
[PATCH 2/6] target/riscv: H extension depends on I extension |
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Date: |
Sun, 10 Jul 2022 16:23:56 +0800 |
- add check for "H depends on an I base integer ISA with 32 x registers"
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dad6906bc..4e40f26e13 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -642,6 +642,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+ error_setg(errp,
+ "H depends on an I base integer ISA with 32 x
registers");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.17.1
- [PATCH 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/10
- [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/10
- [PATCH 5/6] target/riscv: fix checks in hmode/hmode32, Weiwei Li, 2022/07/10
- [PATCH 2/6] target/riscv: H extension depends on I extension,
Weiwei Li <=
- [PATCH 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/10
- [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/10
- [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/10