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Re: [PATCH v2 2/6] target/riscv: H extension depends on I extension
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From: |
Andrew Jones |
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Subject: |
Re: [PATCH v2 2/6] target/riscv: H extension depends on I extension |
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Date: |
Mon, 18 Jul 2022 11:05:33 +0200 |
On Tue, Jul 12, 2022 at 02:32:32PM +0800, Weiwei Li wrote:
> - add check for "H depends on an I base integer ISA with 32 x registers"
Please use a normal sentence without '-'. It'd be nice to write the
doc/version/section of the spec that inspires this check in the
commit message.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 36c1b26fb3..b8ce0959cb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -732,6 +732,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
> + error_setg(errp,
> + "H depends on an I base integer ISA with 32 x
> registers");
> + return;
> + }
> +
> if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> --
> 2.17.1
>
>
Otherwise
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
- Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32, (continued)
- [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/12
- [PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/12
- [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/12
- [PATCH v2 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/12
- Re: [PATCH v2 2/6] target/riscv: H extension depends on I extension,
Andrew Jones <=
- [PATCH v2 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/12