[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32
From: |
Andrew Jones |
Subject: |
Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32 |
Date: |
Mon, 18 Jul 2022 11:26:30 +0200 |
Same other $SUBJECT and comment suggestions as the previous patches.
On Tue, Jul 12, 2022 at 02:32:35PM +0800, Weiwei Li wrote:
> - add check for the implicit dependence between H and S
> - Csrs only existed in RV32 will not trigger virtual instruction fault
> when not in RV32
I think I found the justification for this in 8.6.1 of the privileged
spec, a pointer in the commit message would be good.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/csr.c | 9 ++-------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b8ce0959cb..455787a940 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -738,6 +738,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
> + error_setg(errp, "H extension implicitly requires S-mode");
> + return;
> + }
> +
> if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1edeb69366..deddeb100e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
>
> static RISCVException hmode(CPURISCVState *env, int csrno)
> {
> - if (riscv_has_ext(env, RVS) &&
> - riscv_has_ext(env, RVH)) {
> + if (riscv_has_ext(env, RVH)) {
> /* Hypervisor extension is supported */
> if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
> env->priv == PRV_M) {
> @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int
> csrno)
> static RISCVException hmode32(CPURISCVState *env, int csrno)
> {
> if (riscv_cpu_mxl(env) != MXL_RV32) {
> - if (!riscv_cpu_virt_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - } else {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> + return RISCV_EXCP_ILLEGAL_INST;
> }
>
> return hmode(env, csrno);
> --
> 2.17.1
>
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
- [PATCH v2 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/12
- [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32, Weiwei Li, 2022/07/12
- Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32,
Andrew Jones <=
- [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/12
- [PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/12
- [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/12
- [PATCH v2 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/12