qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContex


From: Alistair Francis
Subject: Re: [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext
Date: Fri, 26 May 2023 12:02:18 +1000

On Wed, May 24, 2023 at 12:16 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Use cur_insn_len to store the length of the current instruction to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1c9a667653..d756866925 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -59,6 +59,7 @@ typedef struct DisasContext {
>      DisasContextBase base;
>      /* pc_succ_insn points to the instruction following base.pc_next */
>      target_ulong pc_succ_insn;
> +    target_ulong cur_insn_len;
>      target_ulong priv_ver;
>      RISCVMXL misa_mxl_max;
>      RISCVMXL xl;
> @@ -1114,8 +1115,9 @@ static void decode_opc(CPURISCVState *env, DisasContext 
> *ctx, uint16_t opcode)
>      };
>
>      ctx->virt_inst_excp = false;
> +    ctx->cur_insn_len = insn_len(opcode);
>      /* Check for compressed insn */
> -    if (insn_len(opcode) == 2) {
> +    if (ctx->cur_insn_len == 2) {
>          ctx->opcode = opcode;
>          ctx->pc_succ_insn = ctx->base.pc_next + 2;
>          /*
> --
> 2.25.1
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]