Re: [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

[Alistair Francis]

On Wed, May 24, 2023 at 12:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Reduce reliance on absolute values(by passing pc difference) to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_privileged.c.inc |  2 +-
>  target/riscv/insn_trans/trans_rvi.c.inc        |  6 +++---
>  target/riscv/insn_trans/trans_rvv.c.inc        |  4 ++--
>  target/riscv/insn_trans/trans_rvzawrs.c.inc    |  2 +-
>  target/riscv/insn_trans/trans_xthead.c.inc     |  2 +-
>  target/riscv/translate.c                       | 10 +++++-----
>  6 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc 
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 7c2837194c..3760fb4393 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -112,7 +112,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
>  {
>  #ifndef CONFIG_USER_ONLY
>      decode_save_opc(ctx);
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      gen_helper_wfi(cpu_env);
>      return true;
>  #else
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 81ed0d200a..f9f4d25cda 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -776,7 +776,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
>       * PAUSE is a no-op in QEMU,
>       * end the TB and return to main loop
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> @@ -800,7 +800,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i 
> *a)
>       * FENCE_I is a no-op in QEMU,
>       * however we need to end the translation block
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>      return true;
> @@ -811,7 +811,7 @@ static bool do_csr_post(DisasContext *ctx)
>      /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
>      decode_save_opc(ctx);
>      /* We may have changed important cpu state -- exit to main loop. */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      exit_tb(ctx);
>      ctx->base.is_jmp = DISAS_NORETURN;
>      return true;
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6c07eebc52..c2f7527f53 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -169,7 +169,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
> TCGv s2)
>      gen_set_gpr(s, rd, dst);
>      mark_vs_dirty(s);
>
> -    gen_set_pc_imm(s, s->pc_succ_insn);
> +    gen_update_pc(s, s->cur_insn_len);
>      lookup_and_goto_ptr(s);
>      s->base.is_jmp = DISAS_NORETURN;
>      return true;
> @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
> TCGv s2)
>      gen_helper_vsetvl(dst, cpu_env, s1, s2);
>      gen_set_gpr(s, rd, dst);
>      mark_vs_dirty(s);
> -    gen_set_pc_imm(s, s->pc_succ_insn);
> +    gen_update_pc(s, s->cur_insn_len);
>      lookup_and_goto_ptr(s);
>      s->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc 
> b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> index 8254e7dfe2..32efbff4d5 100644
> --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
> @@ -33,7 +33,7 @@ static bool trans_wrs(DisasContext *ctx)
>      /* Clear the load reservation  (if any).  */
>      tcg_gen_movi_tl(load_res, -1);
>
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      tcg_gen_exit_tb(NULL, 0);
>      ctx->base.is_jmp = DISAS_NORETURN;
>
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc 
> b/target/riscv/insn_trans/trans_xthead.c.inc
> index 3e13b1d74d..da093a4cec 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -999,7 +999,7 @@ static void gen_th_sync_local(DisasContext *ctx)
>       * Emulate out-of-order barriers with pipeline flush
>       * by exiting the translation block.
>       */
> -    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    gen_update_pc(ctx, ctx->cur_insn_len);
>      tcg_gen_exit_tb(NULL, 0);
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8a371c0d75..b01aa48f04 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -232,14 +232,14 @@ static void gen_pc_plus_diff(TCGv target, DisasContext 
> *ctx,
>      tcg_gen_movi_tl(target, dest);
>  }
>
> -static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
> +static void gen_update_pc(DisasContext *ctx, target_long diff)
>  {
> -    gen_pc_plus_diff(cpu_pc, ctx, dest);
> +    gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
>  }
>
>  static void generate_exception(DisasContext *ctx, int excp)
>  {
> -    gen_set_pc_imm(ctx, ctx->base.pc_next);
> +    gen_update_pc(ctx, 0);
>      gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
>      ctx->base.is_jmp = DISAS_NORETURN;
>  }
> @@ -291,10 +291,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, 
> target_long diff)
>        */
>      if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
>          tcg_gen_goto_tb(n);
> -        gen_set_pc_imm(ctx, dest);
> +        gen_update_pc(ctx, diff);
>          tcg_gen_exit_tb(ctx->base.tb, n);
>      } else {
> -        gen_set_pc_imm(ctx, dest);
> +        gen_update_pc(ctx, diff);
>          lookup_and_goto_ptr(ctx);
>      }
>  }
> --
> 2.25.1
>
>