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[PATCH v2 07/26] s390x/tcg: Simplify vfma64() handling
From: |
David Hildenbrand |
Subject: |
[PATCH v2 07/26] s390x/tcg: Simplify vfma64() handling |
Date: |
Mon, 17 May 2021 16:27:20 +0200 |
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 --
target/s390x/translate_vx.c.inc | 8 +++----
target/s390x/vec_fpu_helper.c | 42 +++++++++++++--------------------
3 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index e832680236..3c87593553 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -267,9 +267,7 @@ DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr,
cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
-DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
-DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 1404471881..4b5bf0a7e3 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2589,7 +2589,6 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
{
const uint8_t m5 = get_field(s, m5);
const uint8_t fpf = get_field(s, m6);
- const bool se = extract32(m5, 3, 1);
gen_helper_gvec_4_ptr *fn;
if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
@@ -2598,13 +2597,12 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps
*o)
}
if (s->fields.op2 == 0x8f) {
- fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64;
+ fn = gen_helper_gvec_vfma64;
} else {
- fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;
+ fn = gen_helper_gvec_vfms64;
}
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4), cpu_env,
- 0, fn);
+ get_field(s, v3), get_field(s, v4), cpu_env, m5, fn);
return DISAS_NEXT;
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 3267067420..29a6d52827 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -376,12 +376,12 @@ static void vfma64(S390Vector *v1, const S390Vector *v2,
const S390Vector *v3,
int i;
for (i = 0; i < 2; i++) {
- const uint64_t a = s390_vec_read_element64(v2, i);
- const uint64_t b = s390_vec_read_element64(v3, i);
- const uint64_t c = s390_vec_read_element64(v4, i);
- uint64_t ret = float64_muladd(a, b, c, flags, &env->fpu_status);
+ const float64 a = s390_vec_read_float64(v2, i);
+ const float64 b = s390_vec_read_float64(v3, i);
+ const float64 c = s390_vec_read_float64(v4, i);
+ const float64 ret = float64_muladd(a, b, c, flags, &env->fpu_status);
- s390_vec_write_element64(&tmp, i, ret);
+ s390_vec_write_float64(&tmp, i, ret);
vxc = check_ieee_exc(env, i, false, &vec_exc);
if (s || vxc) {
break;
@@ -391,29 +391,21 @@ static void vfma64(S390Vector *v1, const S390Vector *v2,
const S390Vector *v3,
*v1 = tmp;
}
-void HELPER(gvec_vfma64)(void *v1, const void *v2, const void *v3,
- const void *v4, CPUS390XState *env, uint32_t desc)
-{
- vfma64(v1, v2, v3, v4, env, false, 0, GETPC());
-}
-
-void HELPER(gvec_vfma64s)(void *v1, const void *v2, const void *v3,
- const void *v4, CPUS390XState *env, uint32_t desc)
-{
- vfma64(v1, v2, v3, v4, env, true, 0, GETPC());
+#define DEF_GVEC_VFMA_B(NAME, FLAGS, BITS)
\
+void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3,
\
+ const void *v4, CPUS390XState *env,
\
+ uint32_t desc)
\
+{
\
+ const bool se = extract32(simd_data(desc), 3, 1);
\
+
\
+ vfma##BITS(v1, v2, v3, v4, env, se, FLAGS, GETPC());
\
}
-void HELPER(gvec_vfms64)(void *v1, const void *v2, const void *v3,
- const void *v4, CPUS390XState *env, uint32_t desc)
-{
- vfma64(v1, v2, v3, v4, env, false, float_muladd_negate_c, GETPC());
-}
+#define DEF_GVEC_VFMA(NAME, FLAGS)
\
+ DEF_GVEC_VFMA_B(NAME, FLAGS, 64)
-void HELPER(gvec_vfms64s)(void *v1, const void *v2, const void *v3,
- const void *v4, CPUS390XState *env, uint32_t desc)
-{
- vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC());
-}
+DEF_GVEC_VFMA(vfma, 0)
+DEF_GVEC_VFMA(vfms, float_muladd_negate_c)
void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env,
uint32_t desc)
--
2.31.1
- [PATCH v2 00/26] s390x/tcg: Implement Vector enhancements facility and switch to z14, David Hildenbrand, 2021/05/17
- [PATCH v2 01/26] s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling, David Hildenbrand, 2021/05/17
- [PATCH v2 04/26] s390x/tcg: Simplify vop64_2() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 02/26] s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED), David Hildenbrand, 2021/05/17
- [PATCH v2 05/26] s390x/tcg: Simplify vfc64() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 03/26] s390x/tcg: Simplify vop64_3() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 07/26] s390x/tcg: Simplify vfma64() handling,
David Hildenbrand <=
- [PATCH v2 08/26] s390x/tcg: Simplify vfll32() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 06/26] s390x/tcg: Simplify vftci64() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 09/26] s390x/tcg: Simplify vflr64() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 10/26] s390x/tcg: Simplify wfc64() handling, David Hildenbrand, 2021/05/17
- [PATCH v2 11/26] s390x/tcg: Implement VECTOR BIT PERMUTE, David Hildenbrand, 2021/05/17
- [PATCH v2 13/26] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT), David Hildenbrand, 2021/05/17
- [PATCH v2 14/26] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT), David Hildenbrand, 2021/05/17
- [PATCH v2 16/26] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2021/05/17
- [PATCH v2 17/26] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, David Hildenbrand, 2021/05/17
- [PATCH v2 18/26] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, David Hildenbrand, 2021/05/17