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Re: [Tinycc-devel] ARM32 gfunc_epilog

From: Daniel Glöckner
Subject: Re: [Tinycc-devel] ARM32 gfunc_epilog
Date: Mon, 10 Oct 2016 19:02:49 +0200
User-agent: Mutt/1.5.20 (2009-06-14)

On Mon, Oct 10, 2016 at 11:46:41AM +0200, Daniel Glöckner wrote:
> It emits the instruction "ldm fp, {fp, sp, pc}" which AFAIK will not
> do what we want when it is restarted after an exception, as the first
> thing it does is to change fp.

After reading all those ARM docs, I get the feeling that this will not
affect us. All existing Cortex-A processors do not support interruptible
LDM/STM as per ID_ISAR2 register and since ARM7EJ-S data aborts use the
base restored data abort model, meaning they restore the base register
to the value it had before the instruction. I have to check what my
Zaurus does. It still uses the base updated data abort model. The old
APCS standard apparently also used "ldmdb fp, {fp, sp, pc}", so it
would have suffered from the same problem.

The ARM11 (RPi!) does indicate support for interruptible LDM/STM in its
ID_ISAR2, but it will not interrupt these instructions unless low
interrupt latency mode is enabled. ARM11 was the first ARM with low
interrupt latency mode. I somehow doubt that Linux can run in this mode.

Generating APCS-compatible stack frames that can be unwound f.ex. by
the Linux OProfile code is easy. Creating the .ARM.extab and .ARM.exidx
sections specified by EABI would be significantly more work.

Best regards,


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