Re: [Tinycc-devel] Anyone else working with the RISC-V port?

[Michael Matz]

Hello Christian,

On Mon, 21 Dec 2020, Christian Jullien wrote:

> tcc Linux/riscv-64 is now part of my OpenLisp compiler non-regression 
> plateform and the result is as good as if compiled with gcc (except of 
> course execution speed). My huge OpenLisp test suite runs flawlessly 
> when using tcc. For my use, this port is fully functional. I use a 
> Gnufarm emulated machine installed with latest Debian. I'm impatient to 
> see a RPi like with riscv-64.
>
> Here is what I can say of the wonderful port made by Michael.

That's all very nice to hear!  Thanks for your kind words :-)


Ciao,
Michael.

> C.
>
> -----Original Message-----
> From: Tinycc-devel [mailto:tinycc-devel-bounces+eligis=orange.fr@nongnu.org] On 
> Behalf Of Michael Matz
> Sent: Sunday, December 20, 2020 23:41
> To: tinycc-devel@nongnu.org
> Subject: Re: [Tinycc-devel] Anyone else working with the RISC-V port?
>
> Hello,
>
> On Sat, 19 Dec 2020, Charles Lohr wrote:
>
> > I am interested in doing a project using TinyCC, a web-based IDE for 
> > the ESP32-C3, a wifi-enabled microcontroller.
> > https://github.com/cnlohr/espwebc3/blob/main/README.md
> >
> > I spent a while trying to decipher riscv-gen, and it's actually not 
> > that bad.  Very much inline with the cryptic TinyCC (ok, bit of a jab, 
> > but it's not that bad).  It currently only supports RV64, vs the chip 
> > I'll be using supports RV32-IMC.  Conveniently, most of the 
> > instructions implemented in riscv-gen are the 32-bit instructions, 
> > only a handful of RV64 instructions, which shouldn't be too difficult to avoid.
>
> Right, that should be relatively easy.  One thing to look out for will probably be the fact that you then need to use the generic code in tcc for open-coding 64bit support (e.g. arithmetic on long long), i.e. 
> lexpand/lbuild/gen_opl, which currently is only tested on i386 and arm32. 
> Look for uses of PTR_SIZE in tccgen.c.
>
> You also need to adjust the linker/object-file-writer to use ELF32 on riscv; 
> that's all supported already of course, but needs the right conditionals and 
> some additional defines/codes for the 32bit relocations (where they really 
> differ from the ELF64 ones).
>
> > Is anyone else working in this area? Has anyone expressed any 
> > possibility at adding a few more comments to the riscv-gen code?
>
> Well, what can I say.  Sure, comments might be nice, if they clarify things :)
>
> > Are there any landmines I may run into?
>
> Not that I know of, it's all fairly straight forward.  I have tested the
> riscv64 backend only relatively lightly, and am not sure if others have played 
> much with it, so it's quite possible you run into genuine bugs therein.
>
> > How eager would people be to add a -m32 flag for RISC-V?
>
> I'd suggest going the same way as i386/x86-64, i.e. create a riscv32-tcc 
> compiler, which can then be called from tcc when -m32 is used.  Supporting both 
> bit-width in the same executable will run into major refactoring work as 
> several types are hard-coded (e.g. the whole ELF support isn't conditionalized 
> at runtime per word width).
>
>
> Ciao,
> Michael.
>
>
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