estimating critical path

[Tuukka Toivonen]

What tools there are to estimate the critical path delay from
a (transistor level) schematics?

At first glance Logical Effort Tool looks useful, but it looks
like it couldn't do it anyway. Does it work only on Layout view or what's
wrong? It says:
        Sorry, cannot analyze pMOS-transistor nodes
        Directionality of path is unknown

I need to know at which clock frequencies a circuit can work.
(And of course ALS has hugely different opinion than IRSIM.
I suppose IRSIM is more reliably because ALS doesn't seem to understand
much about technologies)