Re: estimating critical path

[Steven Rubin]

> What tools there are to estimate the critical path delay from
> a (transistor level) schematics?
>
> At first glance Logical Effort Tool looks useful, but it looks
> like it couldn't do it anyway. Does it work only on Layout view or what's
> wrong? It says:
>         Sorry, cannot analyze pMOS-transistor nodes
>         Directionality of path is unknown
>
> I need to know at which clock frequencies a circuit can work.
> (And of course ALS has hugely different opinion than IRSIM.
> I suppose IRSIM is more reliably because ALS doesn't seem to understand
> much about technologies)

The Logical Effort tool is still in its infancy.  It is really just a 
collection of code snippets to test out the ideas in the Logical Effort 
book.  The "Estimate Delays" command looks at the area of metal and other 
layers and calculates delays.  Therefore, it is useless for schematics.  As 
far as the comment "Directionality of path is unknown" goes, it is trying 
to determine the direction of flow from the input/output nature of 
exports.  Be sure to set it properly.

   -Steve