bus with 32 connected registers?

[Tuukka Toivonen]

I made a (schematic level) design that has 32 registers, each containing
25-bit words. The registers all are connected to a single bus through
transmission gates as inputs, of which only one is open at the same
time, and the other end of the bus is connected to an ALU-like component.

When I use IRSIM to simulate the circuit it looks like a register
wouldn't have power to drive the bus: 0-bits are ok but 1-bits are
changed to X's on the bus. This happens only with linear model, the
switch level simulation gives ok results. When at most 9 registers
are connected to the bus, it works fine but as soon as I connect
10th, it doesn't work anymore.

I'm using scmos100 tech with IRSIM, is that reasonable?

First, is IRSIM simulating it correctly? I thought that closed
transmission gates wouldn't be counted as fanin, but it looks I was wrong.

Second, what to do? I have several books but I can't find help from
them. Can I resize the transistors or should I use multiplexer(s) based
on combinational logic?

Some interesting numbers: the design has about 60.000 transistors and
the generated IRSIM simulation file is about 10 megabytes.
I'm using (basically) two Electric libraries which together take
about 1 MB of space.