Re: Can Electric read in VHDL source files

[Steven Rubin]

At 08:05 PM 11/12/2009, you wrote:
> I am new to the Electric tool. I am curious to know if Electric can read in a
> standard VHDL circuit file, and simulate it, or generate the netlist. Could
> someone please provide some pointers in this regard ? thanks in advance
> for your help.

Electric can read VHDL, compile it to a netlist, and simulate that 
netlist.  The problems with this are (1) it can only handle 
structural VHDL, not behavioral VHDL and (2) its simulator, ALS, is 
old and not as good as some modern ones.

   -Steven Rubin