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[Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction |
Date: |
Tue, 26 Jul 2016 17:28:27 +0530 |
ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ca246ea..7e349e8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -817,6 +817,43 @@ static void gen_cmpli(DisasContext *ctx)
}
}
+/* cmprb - range comparison: isupper, isaplha, islower*/
+static void gen_cmprb(DisasContext *ctx)
+{
+ TCGv_i32 src1 = tcg_temp_new_i32();
+ TCGv_i32 src2 = tcg_temp_new_i32();
+ TCGv_i32 src2lo = tcg_temp_new_i32();
+ TCGv_i32 src2hi = tcg_temp_new_i32();
+ TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
+
+ tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
+
+ tcg_gen_ext8u_i32(src2lo, src2);
+ tcg_gen_shri_i32(src2, src2, 8);
+ tcg_gen_ext8u_i32(src2hi, src2);
+
+ tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
+ tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
+ tcg_gen_and_i32(crf, src2lo, src2hi);
+
+ if (ctx->opcode & 0x00200000) {
+ tcg_gen_shri_i32(src2, src2, 8);
+ tcg_gen_ext8u_i32(src2lo, src2);
+ tcg_gen_shri_i32(src2, src2, 8);
+ tcg_gen_ext8u_i32(src2hi, src2);
+ tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
+ tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
+ tcg_gen_and_i32(src2lo, src2lo, src2hi);
+ tcg_gen_or_i32(crf, crf, src2lo);
+ }
+ tcg_gen_shli_i32(crf, crf, CRF_GT);
+ tcg_temp_free_i32(src1);
+ tcg_temp_free_i32(src2);
+ tcg_temp_free_i32(src2lo);
+ tcg_temp_free_i32(src2hi);
+}
+
/* isel (PowerPC 2.03 specification) */
static void gen_isel(DisasContext *ctx)
{
@@ -9897,6 +9934,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000,
PPC_INTEGER),
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.7.4
- [Qemu-ppc] [PATCH v4 00/15] POWER9 TCG enablements - part1, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 01/15] target-ppc: Introduce Power9 family, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 02/15] target-ppc: Introduce POWER ISA 3.0 flag, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 03/15] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 05/15] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 10/15] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 08/15] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 15/15] target-ppc: introduce opc4 for Expanded Opcode, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 14/15] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/26