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[Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction |
Date: |
Tue, 26 Jul 2016 17:28:36 +0530 |
maddld: Multiply-Add Low Doubleword
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the lower dword in the target
register(RT).
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-ppc/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fa1c28c..81a87e9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7741,6 +7741,17 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
+#if defined(TARGET_PPC64)
+static void gen_maddld(DisasContext *ctx)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
+ tcg_temp_free_i64(t1);
+}
+#endif /* defined(TARGET_PPC64) */
+
GEN_VXFORM_NOA(vclzb, 1, 28)
GEN_VXFORM_NOA(vclzh, 1, 29)
GEN_VXFORM_NOA(vclzw, 1, 30)
@@ -10356,6 +10367,9 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001,
PPC_ALTIVEC),
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
--
2.7.4
- [Qemu-ppc] [PATCH v4 02/15] target-ppc: Introduce POWER ISA 3.0 flag, (continued)
- [Qemu-ppc] [PATCH v4 02/15] target-ppc: Introduce POWER ISA 3.0 flag, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 03/15] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 05/15] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 10/15] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 08/15] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 15/15] target-ppc: introduce opc4 for Expanded Opcode, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 14/15] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH v4 09/15] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH v4 12/15] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH v4 11/15] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/26
Re: [Qemu-ppc] [PATCH v4 00/15] POWER9 TCG enablements - part1, David Gibson, 2016/07/27