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[Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.]
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.] |
Date: |
Tue, 26 Jul 2016 17:28:30 +0530 |
While implementing modulo instructions figured out that the
implementation uses many branches. Change the logic to achieve the
branch-less code. Undefined value is set to dividend in case of invalid
input.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 48 +++++++++++++++++++++++-------------------------
1 file changed, 23 insertions(+), 25 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7c7328f..69d9ae0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1049,41 +1049,39 @@ static void gen_addpcis(DisasContext *ctx)
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGv_i32 t0 = tcg_temp_local_new_i32();
- TCGv_i32 t1 = tcg_temp_local_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, arg1);
tcg_gen_trunc_tl_i32(t1, arg2);
- tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
- if (sign) {
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
- tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
- gen_set_label(l3);
- tcg_gen_div_i32(t0, t0, t1);
- } else {
- tcg_gen_divu_i32(t0, t0, t1);
- }
- if (compute_ov) {
- tcg_gen_movi_tl(cpu_ov, 0);
- }
- tcg_gen_br(l2);
- gen_set_label(l1);
if (sign) {
- tcg_gen_sari_i32(t0, t0, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
+ tcg_gen_and_i32(t2, t2, t3);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
+ tcg_gen_or_i32(t2, t2, t3);
+ tcg_gen_movi_i32(t3, 0);
+ tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_div_i32(t3, t0, t1);
+ tcg_gen_extu_i32_tl(ret, t3);
} else {
- tcg_gen_movi_i32(t0, 0);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
+ tcg_gen_movi_i32(t3, 0);
+ tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_divu_i32(t3, t0, t1);
+ tcg_gen_extu_i32_tl(ret, t3);
}
if (compute_ov) {
- tcg_gen_movi_tl(cpu_ov, 1);
- tcg_gen_movi_tl(cpu_so, 1);
+ tcg_gen_extu_i32_tl(cpu_ov, t2);
+ tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
- gen_set_label(l2);
- tcg_gen_extu_i32_tl(ret, t0);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, ret);
}
--
2.7.4
- [Qemu-ppc] [PATCH v4 03/15] target-ppc: adding addpcis instruction, (continued)
- [Qemu-ppc] [PATCH v4 03/15] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 04/15] target-ppc: add cmprb instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 06/15] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 05/15] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 10/15] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 08/15] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 15/15] target-ppc: introduce opc4 for Expanded Opcode, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 14/15] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 13/15] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.],
Nikunj A Dadhania <=
[Qemu-ppc] [PATCH v4 09/15] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH v4 12/15] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/26
[Qemu-ppc] [PATCH v4 11/15] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/26
Re: [Qemu-ppc] [PATCH v4 00/15] POWER9 TCG enablements - part1, David Gibson, 2016/07/27