Re: [avrdude-dev] ATtiny2313 and pony-stk200 problems?

[Bob Paddock]

> 1) The 1MHz mentioned above is the oscillator frequency of the chip
> *not* the SPI clock.

The Tiny2313 from the factory is running at 500 kHz (4 MHz/8).
The Serial Programming Characteristics says that a minimum of two clock  
cycles
are required which would give a max SPI clock of 250 kHz max.

There is also this comment in the USI section, but there is no indication  
that
the fCK/4 limit of 125 kHz applies to the SPI programming mode?

"Three-wire Synchronous Data Transfer (Master, fSCKmax = fCK/2, Slave  
fSCKmax = fCK/4)"


> 2) The above comment is from the current CVS. Bob is apparently using
> 4.3.0

I built the CVS code a few minutes ago.  I can now read the signature  
every time,
but I still can not verify the flash.  The error is always 0xbe != 0x00 at  
address 0x0000.

Placing the chip back in the STK500 to read it produces this:

:1000000000000000000000000000000000000000F0
:1000100000000000000000000000000000000000E0
:10002000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0
:10003000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
:10004000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0
:10005000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB0
:10006000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0
:10007000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF90
:10008000000000020002000000000000000200006A
:100090000000000000000000000000000000000060
:1000A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60
:1000B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50
:1000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40
:1000D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF30
:1000E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20
:1000F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF10
:10010000000000800080008100810080008001816B
:10011000008100800000008000810001000109B71B
:10012000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF
...

> 1) Timing is a bit different with Linux (or BSD) and Windows.

I am using Cygwin/Windows on a 2.4 GHz P4, if the speed of
the machine has any baring on the timing, I assume it does not.

> So the timing constraints for the SPI interface can be violated even
> if the clock is slow enough.

I have Scope/Logic Analyser setting right here if you have some specific
tests you want me to try.

> The current CVS should work for chips down to 500kHz clock frequency.
> Nevertheless, the margin is not too big.

> Using usleep() is not an option here, because the granularity of a
> sleep is greater than 1ms. Hence, programming will get *very* slow.

To me speed is not that much of an issue with small memory parts like the  
T2313.