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Re: [Help-gnucap] testing verilog netlist input
From: |
John Griessen |
Subject: |
Re: [Help-gnucap] testing verilog netlist input |
Date: |
Mon, 09 Feb 2009 23:53:53 -0600 |
User-agent: |
Mozilla-Thunderbird 2.0.0.17 (X11/20081018) |
I've done a small spice netlist along with two other verilog netlists as a test.
It uses a pulse, but the simulation output stays zeros for all times.
The very last step entering an instance seems to not have the parameters of the
pulse defined...even though they show in a list
in the vpulse module. Here is everything I did, and the gnucap-verilog>list
results:
gnucap-verilog>clear
gnucap-verilog>spice
gnucap-spice>.get ./vpulse.ckt
'pulse volt source
gnucap-spice>.verilog
gnucap-verilog>include verilog_io.net
gnucap-verilog>resistor #(.r(1500) ) R3 ( .n(out), .p(0 ));
gnucap-verilog>verilog_io #(.footprint(none) ) U2 ( .GND(0 ), .IN(in),
.OUT(out))
gnucap-verilog>vpulse V1 (.p(in),.n(0));
gnucap-verilog>list
module vpulse (p,n);
vsource #(pulse.iv( 0.), .pv( 1.), .delay( 1.u), .rise( 1.n), .fall( 1.n),
.width( 5.u), .period(NA( Inf))) V2 (.p(p),.n(n));
endmodule // vpulse
module verilog_io (GND,OUT,IN);
capacitor #(.c( 1.25u)) C1 (.p(B),.n(GND));
inductor #(.l( 0.001)) L1 (.p(B),.n(OUT));
resistor #(.r( 1.K)) R1 (.p(IN),.n(B));
endmodule // verilog_io
resistor #(.r( 1.5K)) R3 (.p(0),.n(out));
verilog_io #(.footprint(none)) U2 (.GND(0),.OUT(out),.IN(in));
vpulse #() V1 (.p(in),.n(0));
gnucap-verilog>
====================run a sim==============================
print tran v(in out)
tran 0 10 .001 trace all >./out.gnucap
this results in
#Time v(in) v(out)
0. 0. 0.
10.E-6 0. 0.
and,
gnucap-verilog>tran 0 10 .0001 trace all >./out.gnucap
gives some transient values changing.
#Time v(in) v(out)
0. 0. 0.
1.E-6 424.E-15 0.
1.001E-6 1. 299.8E-12
1.002E-6 1. 1.4984E-9
1.003E-6 1. 3.8944E-9
1.004E-6 1. 7.4859E-9
So, I have data going in from netlists and a simulation finally.
gnucap-verilog>param shows nothing.
How would I change just the pulse parameters interactively?
John Griessen