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Re: [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR |
Date: |
Wed, 04 Jun 2014 12:29:14 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 6/4/2014 7:50 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined for server
> CPUs in PowerISA 2.07.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
> Changes:
> v5:
> * TIR is defined for servers from 2.07 so it is power8 only
>
> v4:
> * disabled reading it from user space
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 10 ++++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 8955f29..3a578e6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_BOOKE_GIVOR8 (0x1BB)
> #define SPR_BOOKE_GIVOR13 (0x1BC)
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> +#define SPR_TIR (0x1BE)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 7eb02ac..1df69e0 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7518,6 +7518,15 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void gen_spr_power8_ids(CPUPPCState *env)
> +{
> + /* Thread identification */
> + spr_register(env, SPR_TIR, "TIR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> +}
> +
> static void gen_spr_book3s_purr(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -7621,6 +7630,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int
> version)
> }
> if (version >= BOOK3S_CPU_POWER8) {
> gen_spr_power8_tce_address_control(env);
> + gen_spr_power8_ids(env);
> }
> #if !defined(CONFIG_USER_ONLY)
> switch (version) {
>
Reviewed-by: Tom Musta <address@hidden>
- Re: [Qemu-devel] [PATCH v5 07/30] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, (continued)
- [Qemu-devel] [PATCH v5 06/30] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 12/30] target-ppc: Enable PMU SPRs migration, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 10/30] target-ppc: Introduce and reuse generalized init_proc_book3s_64(), Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 14/30] target-ppc: Move POWER8 TCE Address control (TAR) to a helper, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 13/30] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 15/30] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 16/30] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR, Alexey Kardashevskiy, 2014/06/04
- Re: [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR,
Tom Musta <=
- [Qemu-devel] [PATCH v5 17/30] target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 18/30] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 19/30] target-ppc: Refactor class init for POWER7/8, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 25/30] KVM: target-ppc: Enable TM state migration, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 22/30] target-ppc: Enable FSCR facility check for TAR, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/04