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Re: [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration |
Date: |
Wed, 04 Jun 2014 12:30:13 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 6/4/2014 7:51 AM, Alexey Kardashevskiy wrote:
> This hooks SPR with theit "KVM set_one_reg" counterparts which enables
> their migration.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
> target-ppc/translate_init.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 5326553..04390a5 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7399,10 +7399,10 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
> return;
> }
>
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> + spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_VRSAVE, 0x00000000);
>
> /* Can't find information on what this should be on reset. This
> * value is the one used by 74xx processors. */
> @@ -7629,10 +7629,10 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
>
> static void gen_spr_power5p_common(CPUPPCState *env)
> {
> - spr_register(env, SPR_PPR, "PPR",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> + spr_register_kvm(env, SPR_PPR, "PPR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PPR, 0x00000000);
> }
>
> static void gen_spr_power6_common(CPUPPCState *env)
>
Reviewed-by: Tom Musta <address@hidden>
- Re: [Qemu-devel] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, (continued)
- [Qemu-devel] [PATCH v5 22/30] target-ppc: Enable FSCR facility check for TAR, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 30/30] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration, Alexey Kardashevskiy, 2014/06/04
- Re: [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration,
Tom Musta <=
- [Qemu-devel] [PATCH v5 26/30] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 29/30] spapr_hcall: Split h_set_mode(), Alexey Kardashevskiy, 2014/06/04
- Re: [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework, Tom Musta, 2014/06/04
- [Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 02/30] target-ppc: Merge 970FX and 970MP into a single 970 class, Alexey Kardashevskiy, 2014/06/04