[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7 |
Date: |
Wed, 4 Jun 2014 22:51:03 +1000 |
This adds DABRX SPR.
As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
have them (as it implements more powerful facility instead), this limits
DABR/DABRX registration by POWER7 (inclusive).
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
Changes:
v5:
* enabled access for super-mode
* added "TODO" comment
---
target-ppc/translate_init.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 04390a5..85581c9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7411,10 +7411,21 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
static void gen_spr_book3s_dbg(CPUPPCState *env)
{
+ /*
+ * TODO: different specs define different scopes for these,
+ * will have to address this:
+ * 970: super/write and super/read
+ * powerisa 2.03..2.04: hypv/write and super/read.
+ * powerisa 2.05 and newer: hypv/write and hypv/read.
+ */
spr_register_kvm(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
+ spr_register_kvm(env, SPR_DABRX, "DABRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABRX, 0x00000000);
}
static void gen_spr_970_dbg(CPUPPCState *env)
@@ -7793,7 +7804,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
gen_spr_book3s_altivec(env);
gen_spr_book3s_pmu_sup(env);
gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_dbg(env);
gen_spr_book3s_common(env);
switch (version) {
@@ -7837,6 +7847,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
gen_spr_power8_pmu_user(env);
gen_spr_power8_tm(env);
}
+ if (version < BOOK3S_CPU_POWER8) {
+ gen_spr_book3s_dbg(env);
+ }
#if !defined(CONFIG_USER_ONLY)
switch (version) {
case BOOK3S_CPU_970:
--
2.0.0
- [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs, (continued)
- [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 26/30] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs, Alexey Kardashevskiy, 2014/06/04
- [Qemu-devel] [PATCH v5 29/30] spapr_hcall: Split h_set_mode(), Alexey Kardashevskiy, 2014/06/04
- Re: [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework, Tom Musta, 2014/06/04
- [Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7,
Alexey Kardashevskiy <=
- [Qemu-devel] [PATCH v5 02/30] target-ppc: Merge 970FX and 970MP into a single 970 class, Alexey Kardashevskiy, 2014/06/04