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[Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to supp
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers |
Date: |
Thu, 19 Jun 2014 15:45:41 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/machine.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 966c5ef..a51b344 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -26,6 +26,10 @@ static void save_tc(QEMUFile *f, TCState *tc)
qemu_put_betls(f, &tc->CP0_TCScheFBack);
qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
qemu_put_betls(f, &tc->CP0_UserLocal);
+ qemu_put_be32s(f, &tc->last_instr);
+ qemu_put_be32s(f, &tc->CP0_BadInstr);
+ qemu_put_be32s(f, &tc->last_branch);
+ qemu_put_be32s(f, &tc->CP0_BadInstrP);
}
static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
@@ -179,6 +183,10 @@ static void load_tc(QEMUFile *f, TCState *tc, int
version_id)
qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
if (version_id >= 4) {
qemu_get_betls(f, &tc->CP0_UserLocal);
+ qemu_get_be32s(f, &tc->last_instr);
+ qemu_get_be32s(f, &tc->CP0_BadInstr);
+ qemu_get_be32s(f, &tc->last_branch);
+ qemu_get_be32s(f, &tc->CP0_BadInstrP);
}
}
--
1.7.5.4
- Re: [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers, (continued)
- [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers,
Leon Alrae <=
- [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core, Leon Alrae, 2014/06/19