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[Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions |
Date: |
Thu, 19 Jun 2014 15:45:37 +0100 |
An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain XIE bit.
An Read-Inhibit exception occurs when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 5 ++++-
target-mips/helper.c | 25 ++++++++++++++++++++++++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6de51b1..78158bd 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -247,6 +247,7 @@ struct CPUMIPSState {
int32_t CP0_PageGrain;
#define CP0PG_RIE 31
#define CP0PG_XIE 30
+#define CP0PG_IEC 27
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
@@ -648,8 +649,10 @@ enum {
EXCP_C2E,
EXCP_CACHE, /* 32 */
EXCP_DSPDIS,
+ EXCP_TLBXI,
+ EXCP_TLBRI,
- EXCP_LAST = EXCP_DSPDIS,
+ EXCP_LAST = EXCP_TLBRI,
};
/* Dummy exception for conditional stores. */
#define EXCP_SC 0x100
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 643c7cc..e9f31ca 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -254,7 +254,22 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
/* TLB match but 'D' bit is cleared */
exception = EXCP_LTLBL;
break;
-
+ case TLBRET_XI:
+ /* Execute-Inhibit Exception */
+ if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
+ exception = EXCP_TLBXI;
+ } else {
+ exception = EXCP_TLBL;
+ }
+ break;
+ case TLBRET_RI:
+ /* Read-Inhibit Exception */
+ if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
+ exception = EXCP_TLBRI;
+ } else {
+ exception = EXCP_TLBL;
+ }
+ break;
}
/* Raise exception */
env->CP0_BadVAddr = address;
@@ -385,6 +400,8 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_MDMX] = "MDMX",
[EXCP_C2E] = "precise coprocessor 2",
[EXCP_CACHE] = "cache error",
+ [EXCP_TLBXI] = "TLB execute-inhibit",
+ [EXCP_TLBRI] = "TLB read-inhibit",
};
target_ulong exception_resume_pc (CPUMIPSState *env)
@@ -603,6 +620,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_C2E:
cause = 18;
goto set_EPC;
+ case EXCP_TLBRI:
+ cause = 19;
+ goto set_EPC;
+ case EXCP_TLBXI:
+ cause = 20;
+ goto set_EPC;
case EXCP_MDMX:
cause = 22;
goto set_EPC;
--
1.7.5.4
- [Qemu-devel] [PATCH 00/12] implement features required in MIPS64 Release 6, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 01/12] target-mips: add KScratch registers, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions,
Leon Alrae <=
- [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core, Leon Alrae, 2014/06/19