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[Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-gene
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core |
Date: |
Thu, 19 Jun 2014 15:45:42 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate_init.c | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 561eeb0..1f199fd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -357,8 +357,10 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
- .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
+ (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (3 << CP0C4_IE) | (1U << CP0C4_M),
.CP0_Config4_rw_bitmask = 0,
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
@@ -370,6 +372,9 @@ static const mips_def_t mips_defs[] =
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP0_PageGrain = (1 << CP0PG_XIE) | (1 << CP0PG_RIE) | (1 <<
CP0PG_IEC),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_XIE) | (1 << CP0PG_RIE) |
+ (1 << CP0PG_IEC),
.CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x93 << FCR0_PRID),
--
1.7.5.4
- [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers, (continued)
- [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers, Leon Alrae, 2014/06/19
- [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core,
Leon Alrae <=
- [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core, Leon Alrae, 2014/06/19