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[Qemu-devel] [PATCH v2 10/18] target-arm: introduce disas flag for endia
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH v2 10/18] target-arm: introduce disas flag for endianness |
Date: |
Tue, 1 Mar 2016 22:56:14 -0800 |
From: Paolo Bonzini <address@hidden>
Introduce a disas flag for setting the CPU data endianness. This allows
control of the endianness from the CPU state rather than hard-coding it
to TARGET_WORDS_BIGENDIAN.
Signed-off-by: Paolo Bonzini <address@hidden>
[ PC changes:
* Split off as new patch from original:
"target-arm: introduce tbflag for CPSR.E"
* Wrote commit message from scratch
]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Changed since v1:
rename mo_endianness to be_data
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 39 ++++++++++++++++++++++++---------------
target-arm/translate.h | 1 +
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f6dd44b..88b95ab 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11032,6 +11032,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu,
TranslationBlock *tb)
!arm_el_is_aa64(env, 3);
dc->thumb = 0;
dc->sctlr_b = 0;
+ dc->be_data = MO_TE;
dc->condexec_mask = 0;
dc->condexec_cond = 0;
dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 2028908..88f24cb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -924,26 +924,30 @@ static inline void store_reg_from_load(DisasContext *s,
int reg, TCGv_i32 var)
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 addr, int index) \
{ \
- tcg_gen_qemu_ld_i32(val, addr, index, (OPC)); \
+ TCGMemOp opc = (OPC) | s->be_data; \
+ tcg_gen_qemu_ld_i32(val, addr, index, opc); \
}
#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 addr, int index) \
{ \
- tcg_gen_qemu_st_i32(val, addr, index, (OPC)); \
+ TCGMemOp opc = (OPC) | s->be_data; \
+ tcg_gen_qemu_st_i32(val, addr, index, opc); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
TCGv_i32 addr, int index)
{
- tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
+ TCGMemOp opc = MO_Q | s->be_data;
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
TCGv_i32 addr, int index)
{
- tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
+ TCGMemOp opc = MO_Q | s->be_data;
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
}
#else
@@ -952,9 +956,10 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64
val,
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 addr, int index) \
{ \
+ TCGMemOp opc = (OPC) | s->be_data; \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
@@ -962,27 +967,30 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s,
TCGv_i32 val, \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 addr, int index) \
{ \
+ TCGMemOp opc = (OPC) | s->be_data; \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_st_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_st_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
TCGv_i32 addr, int index)
{
+ TCGMemOp opc = MO_Q | s->be_data;
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_ld_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
TCGv_i32 addr, int index)
{
+ TCGMemOp opc = MO_Q | s->be_data;
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_st_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
@@ -990,15 +998,15 @@ static inline void gen_aa32_st64(DisasContext *s,
TCGv_i64 val,
DO_GEN_LD(8s, MO_SB)
DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16s, MO_TESW)
-DO_GEN_LD(16u, MO_TEUW)
-DO_GEN_LD(32u, MO_TEUL)
+DO_GEN_LD(16s, MO_SW)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
/* 'a' variants include an alignment check */
-DO_GEN_LD(16ua, MO_TEUW | MO_ALIGN)
-DO_GEN_LD(32ua, MO_TEUL | MO_ALIGN)
+DO_GEN_LD(16ua, MO_UW | MO_ALIGN)
+DO_GEN_LD(32ua, MO_UL | MO_ALIGN)
DO_GEN_ST(8, MO_UB)
-DO_GEN_ST(16, MO_TEUW)
-DO_GEN_ST(32, MO_TEUL)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
@@ -11322,6 +11330,7 @@ void gen_intermediate_code(CPUARMState *env,
TranslationBlock *tb)
!arm_el_is_aa64(env, 3);
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);
+ dc->be_data = MO_TE;
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 0bdc68c..36bc996 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -17,6 +17,7 @@ typedef struct DisasContext {
int singlestep_enabled;
int thumb;
int sctlr_b;
+ TCGMemOp be_data;
#if !defined(CONFIG_USER_ONLY)
int user;
#endif
--
1.9.1
- [Qemu-devel] [PATCH v2 00/18] ARM big-endian and setend support, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 01/18] linux-user: arm: fix coding style for some linux-user signal functions, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 02/18] linux-user: arm: pass env to get_user_code_*, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 04/18] target-arm: cpu: Move cpu_is_big_endian to header, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 03/18] target-arm: implement SCTLR.B, drop bswap_code, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 05/18] arm: cpu: handle BE32 user-mode as BE, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 06/18] linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE mode, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 07/18] linux-user: arm: handle CPSR.E correctly in strex emulation, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 08/18] target-arm: implement SCTLR.EE, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 10/18] target-arm: introduce disas flag for endianness,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v2 09/18] target-arm: pass DisasContext to gen_aa32_ld*/st*, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 11/18] target-arm: a64: Add endianness support, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 12/18] target-arm: introduce tbflag for endianness, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 13/18] target-arm: implement setend, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 15/18] loader: add API to load elf header, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 16/18] loader: load_elf(): Add doc comment, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 17/18] loader: Add data swap option to load-elf, Peter Crosthwaite, 2016/03/02
- [Qemu-devel] [PATCH v2 18/18] arm: boot: Support big-endian elfs, Peter Crosthwaite, 2016/03/02