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[Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide |
Date: |
Tue, 22 Mar 2016 14:46:21 +0100 |
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
---
target-tricore/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 8c429c5..bccdcc3 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7013,45 +7013,51 @@ static void decode_rrr_divide(CPUTriCoreState *env,
DisasContext *ctx)
r3 = MASK_OP_RRR_S3(ctx->opcode);
r4 = MASK_OP_RRR_D(ctx->opcode);
- CHECK_REG_PAIR(r3);
-
switch (op2) {
case OPC2_32_RRR_DVADJ:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP_U:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX_U:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN_U:
+ CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_PACK:
+ CHECK_REG_PAIR(r3);
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
--
2.7.4
- [Qemu-devel] [PULL 00/10] tricore-patches, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 07/10] target-tricore: Add mul.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 01/10] target-tricore: add missing break in insn decode switch stmt, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 04/10] target-tricore: Add FPU infrastructure, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 10/10] target-tricore: Add ftoi and itof instructions, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 09/10] target-tricore: Add cmp.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 03/10] target-tricore: Fix psw_read() clearing too many bits, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 06/10] target-tricore: add add.f/sub.f instructions, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 02/10] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit, Bastian Koppelmann, 2016/03/22
- Re: [Qemu-devel] [PULL 00/10] tricore-patches, Peter Maydell, 2016/03/22