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[Qemu-devel] [PULL 10/10] target-tricore: Add ftoi and itof instructions
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 10/10] target-tricore: Add ftoi and itof instructions |
Date: |
Tue, 22 Mar 2016 14:46:26 +0100 |
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
---
target-tricore/fpu_helper.c | 34 ++++++++++++++++++++++++++++++++++
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++++++
3 files changed, 42 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 6586020..71735af 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -191,3 +191,37 @@ uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1,
uint32_t r2)
set_flush_inputs_to_zero(1, &env->fp_status);
return result;
}
+
+uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ int32_t result, flags;
+
+ result = float32_to_int32(f_arg, &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags) {
+ if (float32_is_any_nan(f_arg)) {
+ result = 0;
+ }
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return (uint32_t)result;
+}
+
+uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_result;
+ uint32_t flags;
+ f_result = int32_to_float32(arg, &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return (uint32_t)f_result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 489530f..9333e16 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -110,6 +110,8 @@ DEF_HELPER_3(fsub, i32, env, i32, i32)
DEF_HELPER_3(fmul, i32, env, i32, i32)
DEF_HELPER_3(fdiv, i32, env, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
+DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(itof, i32, env, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 34cae63..912bf22 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6681,6 +6681,12 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_FTOI:
+ gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
+ case OPC2_32_RR_ITOF:
+ gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.7.4
- [Qemu-devel] [PULL 00/10] tricore-patches, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 07/10] target-tricore: Add mul.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 01/10] target-tricore: add missing break in insn decode switch stmt, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 04/10] target-tricore: Add FPU infrastructure, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 10/10] target-tricore: Add ftoi and itof instructions,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 09/10] target-tricore: Add cmp.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 03/10] target-tricore: Fix psw_read() clearing too many bits, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 06/10] target-tricore: add add.f/sub.f instructions, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 02/10] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit, Bastian Koppelmann, 2016/03/22
- Re: [Qemu-devel] [PULL 00/10] tricore-patches, Peter Maydell, 2016/03/22