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[Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction |
Date: |
Tue, 22 Mar 2016 14:46:24 +0100 |
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
---
target-tricore/fpu_helper.c | 26 ++++++++++++++++++++++++++
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 30 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 885b1c9..eca63eb 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -142,3 +142,29 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1,
uint32_t r2)
return (uint32_t)f_result;
}
+
+uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
+{
+ uint32_t flags;
+ float32 arg1 = make_float32(r1);
+ float32 arg2 = make_float32(r2);
+ float32 f_result;
+
+ f_result = float32_div(arg1, arg2 , &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags) {
+ /* If the output is a NaN, but the inputs aren't,
+ we return a unique value. */
+ if ((flags & float_flag_invalid)
+ && !float32_is_any_nan(arg1)
+ && !float32_is_any_nan(arg2)) {
+ f_result = DIV_NAN;
+ }
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return (uint32_t)f_result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index ac41190..f5eff36 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -108,6 +108,7 @@ DEF_HELPER_1(unpack, i64, i32)
DEF_HELPER_3(fadd, i32, env, i32, i32)
DEF_HELPER_3(fsub, i32, env, i32, i32)
DEF_HELPER_3(fmul, i32, env, i32, i32)
+DEF_HELPER_3(fdiv, i32, env, i32, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 3dadb17..eaa7dd5 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6675,6 +6675,9 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RR_MUL_F:
gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_DIV_F:
+ gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.7.4
- [Qemu-devel] [PULL 00/10] tricore-patches, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 07/10] target-tricore: Add mul.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 01/10] target-tricore: add missing break in insn decode switch stmt, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 04/10] target-tricore: Add FPU infrastructure, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 10/10] target-tricore: Add ftoi and itof instructions, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 09/10] target-tricore: Add cmp.f instruction, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 03/10] target-tricore: Fix psw_read() clearing too many bits, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 06/10] target-tricore: add add.f/sub.f instructions, Bastian Koppelmann, 2016/03/22
- [Qemu-devel] [PULL 02/10] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit, Bastian Koppelmann, 2016/03/22
- Re: [Qemu-devel] [PULL 00/10] tricore-patches, Peter Maydell, 2016/03/22