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[Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match H
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW |
Date: |
Mon, 1 Jul 2019 17:39:05 +0100 |
From: Andrey Smirnov <address@hidden>
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:
* INTD/MSI 122
* INTC 123
* INTB 124
* INTA 125
Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.
(Reference: Linux kernel commit 538d6e9d597584e80 from an
NXP employee confirming that the datasheet is incorrect and
with a report of a test against hardware.)
Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added ref to kernel commit confirming the datasheet error]
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/fsl-imx7.h | 8 ++++----
hw/pci-host/designware.c | 6 ++++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 09f4f33f6e5..8003d45d1e5 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -213,10 +213,10 @@ enum FslIMX7IRQs {
FSL_IMX7_USB2_IRQ = 42,
FSL_IMX7_USB3_IRQ = 40,
- FSL_IMX7_PCI_INTA_IRQ = 122,
- FSL_IMX7_PCI_INTB_IRQ = 123,
- FSL_IMX7_PCI_INTC_IRQ = 124,
- FSL_IMX7_PCI_INTD_IRQ = 125,
+ FSL_IMX7_PCI_INTA_IRQ = 125,
+ FSL_IMX7_PCI_INTB_IRQ = 124,
+ FSL_IMX7_PCI_INTC_IRQ = 123,
+ FSL_IMX7_PCI_INTD_IRQ = 122,
FSL_IMX7_UART7_IRQ = 126,
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 931cd954e87..9ae8c0deb75 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -51,6 +51,8 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
+#define DESIGNWARE_PCIE_IRQ_MSI 3
+
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
@@ -67,7 +69,7 @@ static void designware_pcie_root_msi_write(void *opaque,
hwaddr addr,
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
- qemu_set_irq(host->pci.irqs[0], 1);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
}
}
@@ -311,7 +313,7 @@ static void designware_pcie_root_config_write(PCIDevice *d,
uint32_t address,
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
root->msi.intr[0].status ^= val;
if (!root->msi.intr[0].status) {
- qemu_set_irq(host->pci.irqs[0], 0);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
}
break;
--
2.20.1
- [Qemu-devel] [PULL 00/46] target-arm queue, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 16/46] aspeed/timer: Status register contains reload for stopped timer, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 39/46] target/arm: Move TLB related routines to tlb_helper.c, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 30/46] target/arm: Makefile cleanup (KVM), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 26/46] hw/arm: Add arm SBSA reference machine, skeleton part, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW,
Peter Maydell <=
- [Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container, Peter Maydell, 2019/07/01