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[Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container |
Date: |
Mon, 1 Jul 2019 17:39:17 +0100 |
From: Cédric Le Goater <address@hidden>
The RAM memory region is defined after the SoC is realized when the
SDMC controller has checked that the defined RAM size for the machine
is correct. This is problematic for controller models requiring a link
on the RAM region, for DMA support in the SMC controller for instance.
Introduce a container memory region for the RAM that we can link into
the controllers early, before the SoC is realized. It will be
populated with the RAM region after the checks have be done.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/aspeed.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 5d73267da16..7f01df1b61d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -33,6 +33,7 @@ static struct arm_boot_info aspeed_board_binfo = {
struct AspeedBoardState {
AspeedSoCState soc;
+ MemoryRegion ram_container;
MemoryRegion ram;
MemoryRegion max_ram;
};
@@ -159,6 +160,10 @@ static void aspeed_board_init(MachineState *machine,
ram_addr_t max_ram_size;
bmc = g_new0(AspeedBoardState, 1);
+
+ memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
+ UINT32_MAX);
+
object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
(sizeof(bmc->soc)), cfg->soc_name, &error_abort,
NULL);
@@ -193,16 +198,16 @@ static void aspeed_board_init(MachineState *machine,
&error_abort);
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
+ memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
memory_region_add_subregion(get_system_memory(),
- sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
+ sc->info->memmap[ASPEED_SDRAM],
+ &bmc->ram_container);
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
&error_abort);
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
"max_ram", max_ram_size - ram_size);
- memory_region_add_subregion(get_system_memory(),
- sc->info->memmap[ASPEED_SDRAM] + ram_size,
- &bmc->max_ram);
+ memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
--
2.20.1
- [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW, (continued)
- [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container,
Peter Maydell <=
- [Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7, Peter Maydell, 2019/07/01