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[Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally |
Date: |
Mon, 1 Jul 2019 17:39:03 +0100 |
From: Andrey Smirnov <address@hidden>
Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:
!!root->msi.intr[0].enable ^ !!val;
so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.
Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/pci-host/designware.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 0fdfff57848..ec697c8f9df 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -297,16 +297,10 @@ static void designware_pcie_root_config_write(PCIDevice
*d, uint32_t address,
root->msi.base |= (uint64_t)val << 32;
break;
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
-
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
root->msi.intr[0].enable = val;
-
- if (update_msi_mapping) {
- designware_pcie_root_update_msi_mapping(root);
- }
+ designware_pcie_root_update_msi_mapping(root);
break;
- }
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
root->msi.intr[0].mask = val;
--
2.20.1
- [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part, (continued)
- [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally,
Peter Maydell <=
- [Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 11/46] hw: timer: Add ASPEED RTC device, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 15/46] aspeed/timer: Fix behaviour running Linux, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 03/46] hw/arm/virt: Add support for Cortex-A7, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 04/46] i.mx7d: Add no-op/unimplemented APBH DMA module, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes, Peter Maydell, 2019/07/01