Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

[Peter Maydell]

On Tue, 9 Jul 2019 at 17:58, Lucien Murray-Pitts
<address@hidden> wrote:
> On Mon, Jul 1, 2019 at 9:11 PM Peter Maydell <address@hidden> wrote:
>> > Yes, that's a known bug for arm -- we treat "single step" as
>> > "execute one instruction", whereas I think most debuggers will
>> > treat "we took an exception" as a reason to stop the single step
>> > and return control to the user, rather than executing the insn at
>> > the exception entry point as the one instruction of the step.
>> > (You can see similar odd behaviour if you try to single step a
>> > load instruction which causes a data abort, for instance -- on
>> > arm at least we will execute the first insn of the data abort
>> > handler before completing the step.)

> As recommended in the previous email this is fixable with a call to handle 
> debug
> when were in single step -  I will submit that patch if nobody else it 
> working on this?

I don't think anybody else is, so go ahead.

> Any suggestions on how to obtain pc_next from the "m68k_cpu_do_interrupt( 
> CPUState *cs)" ?

You can't -- pc_next exists only at translate time, and the do_interrupt
function is called at run time. What do_interrupt needs to do is look
at (a) the current state of the CPU and (b) whatever has been stashed
in the exception frame, and then update the state of the CPU accordingly.

thanks
-- PMM