Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

[Richard Henderson]

On 7/10/19 7:50 PM, Lucien Murray-Pitts wrote:
> 
> 
>> On Wed, Jul 10, 2019 at 4:04 AM Richard Henderson
> <address@hidden <mailto:address@hidden>> wrote:
> 
>     > I did have a suggestion.  It was fairly detailed.
>     > https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06522.html
> 
> Your solution is elegant at about 10 lines that return getl_ilen(pc), but it
> seems the s390 has a far simpler 
> instruction word format than the m68k. 

S390 is simpler, in that it encodes the total length into the first two bits of
the opcode.  That said, the same technique can apply.  The only difference is
the location at which you would record the length.

For s390, we do this immediately after loading the entire instruction, having
parsed the length as you saw.

For m68k, we would do this after decoding the entire instruction, as
pc_at_insn_end - pc_at_insn_start.

> However then that got me to thinking, it seems that we can call a portion of
> the TCG system to disassemble a single instruction.
>     TranslationBlock tb;
>     tb.pc = env->pc;
>     gen_intermediate_code(cs, &tb, /* max isn */ 1);
>     int ilen = tb.size;
>     printf( "PC: %08x sz:%08x\n", env->pc, tb, ilen ) ;
> 
> I am very new to TCG, so it does seem there is a lot of code in the
> translator_loop that appears to be interacting with the CPU model/state.
> Should I be worried about this, or is this a safe function to call outside of
> the translator core proper? 

No, it is not safe to call outside of the translator core, because of how this
interacts with emitting tcg opcodes.


r~