Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

[Peter Maydell]

On Mon, 1 Jul 2019 at 13:04, Lucien Anti-Spam
<address@hidden> wrote:
> Further to my initial problem I noticed that TRAP #0 also jumps to the 
> handlers +1 instruction.
> Same behavior can also be seen with ARM "SWI #0".    (PC shows 0x0C vs the 
> expected 0x08)

Yes, that's a known bug for arm -- we treat "single step" as
"execute one instruction", whereas I think most debuggers will
treat "we took an exception" as a reason to stop the single step
and return control to the user, rather than executing the insn at
the exception entry point as the one instruction of the step.
(You can see similar odd behaviour if you try to single step a
load instruction which causes a data abort, for instance -- on
arm at least we will execute the first insn of the data abort
handler before completing the step.)

thanks
-- PMM