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Re: [Qemu-devel] [EXTERNAL][PATCH v8 10/37] target/mips: Style improveme
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From: |
Aleksandar Rikalo |
|
Subject: |
Re: [Qemu-devel] [EXTERNAL][PATCH v8 10/37] target/mips: Style improvements in helper.c |
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Date: |
Mon, 19 Aug 2019 14:40:35 +0000 |
> From: Aleksandar Markovic <address@hidden>
> Sent: Monday, August 19, 2019 2:07 PM
> To: address@hidden <address@hidden>
> Cc: address@hidden <address@hidden>; Aleksandar Markovic <address@hidden>;
> Aleksandar Rikalo <address@hidden>
> Subject: [EXTERNAL][PATCH v8 10/37] target/mips: Style improvements in
> helper.c
>
> From: Aleksandar Markovic <address@hidden>
>
> Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> target/mips/helper.c | 98
> ++++++++++++++++++++++++++++++++--------------------
> 1 file changed, 60 insertions(+), 38 deletions(-)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index 6e583d3..d7a2c77 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -39,8 +39,8 @@ enum {
> #if !defined(CONFIG_USER_ONLY)
>
> /* no MMU emulation */
> -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type)
> +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type)
> {
> *physical = address;
> *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr
> *physical, int *prot,
> }
>
> /* fixed mapping MMU emulation */
> -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type)
> +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type)
> {
> if (address <= (int32_t)0x7FFFFFFFUL) {
> - if (!(env->CP0_Status & (1 << CP0St_ERL)))
> + if (!(env->CP0_Status & (1 << CP0St_ERL))) {
> *physical = address + 0x40000000UL;
> - else
> + } else {
> *physical = address;
> - } else if (address <= (int32_t)0xBFFFFFFFUL)
> + }
> + } else if (address <= (int32_t)0xBFFFFFFFUL) {
> *physical = address & 0x1FFFFFFF;
> - else
> + } else {
> *physical = address;
> + }
>
> *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> return TLBRET_MATCH;
> }
>
> /* MIPS32/MIPS64 R4000-style MMU emulation */
> -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type)
> +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type)
> {
> uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
> uint32_t MMID = env->CP0_MemoryMapID;
> @@ -105,8 +107,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical,
> int *prot,
> if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
> *physical = tlb->PFN[n] | (address & (mask >> 1));
> *prot = PAGE_READ;
> - if (n ? tlb->D1 : tlb->D0)
> + if (n ? tlb->D1 : tlb->D0) {
> *prot |= PAGE_WRITE;
> + }
> if (!(n ? tlb->XI1 : tlb->XI0)) {
> *prot |= PAGE_EXEC;
> }
> @@ -136,9 +139,10 @@ static int is_seg_am_mapped(unsigned int am, bool eu,
> int mmu_idx)
> int32_t adetlb_mask;
>
> switch (mmu_idx) {
> - case 3 /* ERL */:
> - /* If EU is set, always unmapped */
> + case 3:
> + /* ERL */
> if (eu) {
> + /* If EU is set, always unmapped */
> return 0;
> }
> /* fall through */
> @@ -210,7 +214,7 @@ static int get_segctl_physical_address(CPUMIPSState *env,
> hwaddr *physical,
> pa & ~(hwaddr)segmask);
> }
>
> -static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
> +static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
> int *prot, target_ulong real_address,
> int rw, int access_type, int mmu_idx)
> {
> @@ -265,7 +269,8 @@ static int get_physical_address (CPUMIPSState *env,
> hwaddr *physical,
> } else if (address < 0x4000000000000000ULL) {
> /* xuseg */
> if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
> - ret = env->tlb->map_address(env, physical, prot, real_address,
> rw, access_type);
> + ret = env->tlb->map_address(env, physical, prot, real_address,
> rw,
> + access_type);
> } else {
> ret = TLBRET_BADADDR;
> }
> @@ -273,7 +278,8 @@ static int get_physical_address (CPUMIPSState *env,
> hwaddr *physical,
> /* xsseg */
> if ((supervisor_mode || kernel_mode) &&
> SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
> - ret = env->tlb->map_address(env, physical, prot, real_address,
> rw, access_type);
> + ret = env->tlb->map_address(env, physical, prot, real_address,
> rw,
> + access_type);
> } else {
> ret = TLBRET_BADADDR;
> }
> @@ -313,7 +319,8 @@ static int get_physical_address (CPUMIPSState *env,
> hwaddr *physical,
> /* xkseg */
> if (kernel_mode && KX &&
> address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
> - ret = env->tlb->map_address(env, physical, prot, real_address,
> rw, access_type);
> + ret = env->tlb->map_address(env, physical, prot, real_address,
> rw,
> + access_type);
> } else {
> ret = TLBRET_BADADDR;
> }
> @@ -669,7 +676,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t
> *vaddr,
> }
>
> static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
> - int mmu_idx)
> + int mmu_idx)
> {
> int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
> int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
> @@ -951,7 +958,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> }
>
> #ifndef CONFIG_USER_ONLY
> -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
> int rw)
> +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
> + int rw)
> {
> hwaddr physical;
> int prot;
> @@ -1011,7 +1019,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
> };
> #endif
>
> -target_ulong exception_resume_pc (CPUMIPSState *env)
> +target_ulong exception_resume_pc(CPUMIPSState *env)
> {
> target_ulong bad_pc;
> target_ulong isa_mode;
> @@ -1019,8 +1027,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
> isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
> bad_pc = env->active_tc.PC | isa_mode;
> if (env->hflags & MIPS_HFLAG_BMASK) {
> - /* If the exception was raised from a delay slot, come back to
> - the jump. */
> + /*
> + * If the exception was raised from a delay slot, come back to
> + * the jump.
> + */
> bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
> }
>
> @@ -1102,10 +1112,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
> switch (cs->exception_index) {
> case EXCP_DSS:
> env->CP0_Debug |= 1 << CP0DB_DSS;
> - /* Debug single step cannot be raised inside a delay slot and
> - resume will always occur on the next instruction
> - (but we assume the pc has always been updated during
> - code translation). */
> + /*
> + * Debug single step cannot be raised inside a delay slot and
> + * resume will always occur on the next instruction
> + * (but we assume the pc has always been updated during
> + * code translation).
> + */
> env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
> goto enter_debug_mode;
> case EXCP_DINT:
> @@ -1117,7 +1129,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
> case EXCP_DBp:
> env->CP0_Debug |= 1 << CP0DB_DBp;
> /* Setup DExcCode - SDBBP instruction */
> - env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 <<
> CP0DB_DEC;
> + env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
> + (9 << CP0DB_DEC);
> goto set_DEPC;
> case EXCP_DDBS:
> env->CP0_Debug |= 1 << CP0DB_DDBS;
> @@ -1138,8 +1151,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
> env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
> env->hflags &= ~(MIPS_HFLAG_KSU);
> /* EJTAG probe trap enable is not implemented... */
> - if (!(env->CP0_Status & (1 << CP0St_EXL)))
> + if (!(env->CP0_Status & (1 << CP0St_EXL))) {
> env->CP0_Cause &= ~(1U << CP0Ca_BD);
> + }
> env->active_tc.PC = env->exception_base + 0x480;
> set_hflags_for_handler(env);
> break;
> @@ -1165,8 +1179,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
> }
> env->hflags |= MIPS_HFLAG_CP0;
> env->hflags &= ~(MIPS_HFLAG_KSU);
> - if (!(env->CP0_Status & (1 << CP0St_EXL)))
> + if (!(env->CP0_Status & (1 << CP0St_EXL))) {
> env->CP0_Cause &= ~(1U << CP0Ca_BD);
> + }
> env->active_tc.PC = env->exception_base;
> set_hflags_for_handler(env);
> break;
> @@ -1182,12 +1197,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
> uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >>
> CP0Ca_IP;
>
> if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> - /* For VEIC mode, the external interrupt controller feeds
> - * the vector through the CP0Cause IP lines. */
> + /*
> + * For VEIC mode, the external interrupt controller feeds
> + * the vector through the CP0Cause IP lines.
> + */
> vector = pending;
> } else {
> - /* Vectored Interrupts
> - * Mask with Status.IM7-IM0 to get enabled interrupts. */
> + /*
> + * Vectored Interrupts
> + * Mask with Status.IM7-IM0 to get enabled interrupts.
> + */
> pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
> /* Find the highest-priority interrupt. */
> while (pending >>= 1) {
> @@ -1360,7 +1379,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
>
> env->active_tc.PC += offset;
> set_hflags_for_handler(env);
> - env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause <<
> CP0Ca_EC);
> + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
> + (cause << CP0Ca_EC);
> break;
> default:
> abort();
> @@ -1396,7 +1416,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int
> interrupt_request)
> }
>
> #if !defined(CONFIG_USER_ONLY)
> -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
> {
> CPUState *cs = env_cpu(env);
> r4k_tlb_t *tlb;
> @@ -1421,9 +1441,11 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx,
> int use_extra)
> }
>
> if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
> - /* For tlbwr, we can shadow the discarded entry into
> - a new (fake) TLB entry, as long as the guest can not
> - tell that it's there. */
> + /*
> + * For tlbwr, we can shadow the discarded entry into
> + * a new (fake) TLB entry, as long as the guest can not
> + * tell that it's there.
> + */
> env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
> env->tlb->tlb_in_use++;
> return;
> --
> 2.7.4
>
Reviewed-by: Aleksandar Rikalo <address@hidden>
- [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in cpu.c, (continued)
- [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in cpu.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 02/37] target/mips: Amend CP0 WatchHi register implementation, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 03/37] target/mips: Amend CP0 MemoryMapID register implementation, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 09/37] target/mips: Style improvements in machine.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 08/37] target/mips: Style improvements in internal.h, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 01/37] target/mips: Add support for DSPRAM, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 10/37] target/mips: Style improvements in helper.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 04/37] target/mips: Add support for emulation of GINVT instruction, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 12/37] target/mips: Style improvements in cps.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 16/37] target/mips: Style improvements in mips_mipssim.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 13/37] target/mips: Style improvements in mips_fulong2e.c, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 05/37] target/mips: Add support for emulation of CRC32 group of instructions, Aleksandar Markovic, 2019/08/19
- [Qemu-devel] [PATCH v8 14/37] target/mips: Style improvements in mips_int.c, Aleksandar Markovic, 2019/08/19