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[PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN
From: |
Peter Maydell |
Subject: |
[PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN |
Date: |
Tue, 22 Oct 2019 14:31:14 +0100 |
From: Richard Henderson <address@hidden>
There are 3 conditions that each enable this flag. M-profile always
enables; A-profile with EL1 as AA64 always enables. Both of these
conditions can easily be cached. The final condition relies on the
FPEXC register which we are not prepared to cache.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 +-
target/arm/helper.c | 14 ++++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4d961474ce7..9909ff89d4f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
* the same thing as the current security state of the processor!
*/
FIELD(TBFLAG_A32, NS, 6, 1)
-FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */
+FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
/* For M profile only, set if FPCCR.LSPACT is set */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 398e5f5d6df..89aa6fd9339 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env,
int fp_el,
{
uint32_t flags = 0;
+ /* v8M always enables the fpu. */
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
+
if (arm_v7m_is_handler_mode(env)) {
flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
}
@@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env,
int fp_el,
ARMMMUIdx mmu_idx)
{
uint32_t flags = rebuild_hflags_aprofile(env);
+
+ if (arm_el_is_aa64(env, 1)) {
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
+ }
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
@@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
env->vfp.vec_stride);
}
+ if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
+ flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
+ }
}
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
- if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
- || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
- flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
- }
pstate_for_ss = env->uncached_cpsr;
}
--
2.20.1
- [PULL 13/41] target/arm: Split out rebuild_hflags_common_32, (continued)
- [PULL 13/41] target/arm: Split out rebuild_hflags_common_32, Peter Maydell, 2019/10/22
- [PULL 12/41] target/arm: Split out rebuild_hflags_a64, Peter Maydell, 2019/10/22
- [PULL 14/41] target/arm: Split arm_cpu_data_is_big_endian, Peter Maydell, 2019/10/22
- [PULL 16/41] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 15/41] target/arm: Split out rebuild_hflags_m32, Peter Maydell, 2019/10/22
- [PULL 17/41] target/arm: Split out rebuild_hflags_a32, Peter Maydell, 2019/10/22
- [PULL 18/41] target/arm: Split out rebuild_hflags_aprofile, Peter Maydell, 2019/10/22
- [PULL 19/41] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 20/41] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 22/41] target/arm: Add arm_rebuild_hflags, Peter Maydell, 2019/10/22
- [PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN,
Peter Maydell <=
- [PULL 23/41] target/arm: Split out arm_mmu_idx_el, Peter Maydell, 2019/10/22
- [PULL 25/41] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}), Peter Maydell, 2019/10/22
- [PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 26/41] target/arm: Rebuild hflags at EL changes, Peter Maydell, 2019/10/22
- [PULL 27/41] target/arm: Rebuild hflags at MSR writes, Peter Maydell, 2019/10/22
- [PULL 28/41] target/arm: Rebuild hflags at CPSR writes, Peter Maydell, 2019/10/22
- [PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes, Peter Maydell, 2019/10/22
- [PULL 30/41] target/arm: Rebuild hflags for M-profile, Peter Maydell, 2019/10/22
- [PULL 31/41] target/arm: Rebuild hflags for M-profile NVIC, Peter Maydell, 2019/10/22
- [PULL 32/41] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22