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[PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes
From: |
Peter Maydell |
Subject: |
[PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes |
Date: |
Tue, 22 Oct 2019 14:31:22 +0100 |
From: Richard Henderson <address@hidden>
Continue setting, but not relying upon, env->hflags.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index aae7b62458f..c55783e5406 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4174,6 +4174,16 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu));
+
+ if (ri->type & ARM_CP_SUPPRESS_TB_END) {
+ /*
+ * Normally we would always end the TB on an SCTLR write; see the
+ * comment in ARMCPRegInfo sctlr initialization below for why Xscale
+ * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
+ * of hflags from the translator, so do it here.
+ */
+ arm_rebuild_hflags(env);
+ }
}
static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PULL 19/41] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state, (continued)
- [PULL 19/41] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 20/41] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 22/41] target/arm: Add arm_rebuild_hflags, Peter Maydell, 2019/10/22
- [PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN, Peter Maydell, 2019/10/22
- [PULL 23/41] target/arm: Split out arm_mmu_idx_el, Peter Maydell, 2019/10/22
- [PULL 25/41] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}), Peter Maydell, 2019/10/22
- [PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 26/41] target/arm: Rebuild hflags at EL changes, Peter Maydell, 2019/10/22
- [PULL 27/41] target/arm: Rebuild hflags at MSR writes, Peter Maydell, 2019/10/22
- [PULL 28/41] target/arm: Rebuild hflags at CPSR writes, Peter Maydell, 2019/10/22
- [PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes,
Peter Maydell <=
- [PULL 30/41] target/arm: Rebuild hflags for M-profile, Peter Maydell, 2019/10/22
- [PULL 31/41] target/arm: Rebuild hflags for M-profile NVIC, Peter Maydell, 2019/10/22
- [PULL 32/41] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 33/41] hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions, Peter Maydell, 2019/10/22
- [PULL 34/41] hw/sd/sdhci: Add dummy Samsung SDHCI controller, Peter Maydell, 2019/10/22
- [PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller, Peter Maydell, 2019/10/22
- [PULL 36/41] hw/arm/xilinx_zynq: Use the IEC binary prefix definitions, Peter Maydell, 2019/10/22
- [PULL 37/41] hw/arm/mps2: Use the IEC binary prefix definitions, Peter Maydell, 2019/10/22
- [PULL 38/41] hw/arm/collie: Create the RAM in the board, Peter Maydell, 2019/10/22
- [PULL 39/41] hw/arm/omap2: Create the RAM in the board, Peter Maydell, 2019/10/22