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[PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
From: |
Peter Maydell |
Subject: |
[PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller |
Date: |
Tue, 22 Oct 2019 14:31:28 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
The Exynos SoC has specific SDHCI registers. Use the s3c SDHCI
model which handle these specific registers.
This silents the following "SDHC ... not implemented" warnings so
we can focus on the important registers missing:
$ qemu-system-arm ... -d unimp \
-append "... root=/dev/mmcblk0 rootfstype=ext4 rw rootwait" \
-drive file=linux-build-test/rootfs/arm/rootfs-armv5.ext2,if=sd,format=raw
[...]
[ 25.744858] sdhci: Secure Digital Host Controller Interface driver
[ 25.745862] sdhci: Copyright(c) Pierre Ossman
[ 25.783188] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2
(12000000 Hz)
SDHC rd_4b @0x80 not implemented
SDHC wr_4b @0x80 <- 0x00000020 not implemented
SDHC wr_4b @0x8c <- 0x00030000 not implemented
SDHC rd_4b @0x80 not implemented
SDHC wr_4b @0x80 <- 0xc0004100 not implemented
SDHC wr_4b @0x84 <- 0x80808080 not implemented
[ 26.013318] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using
ADMA
[ 26.032318] Synopsys Designware Multimedia Card Interface Driver
[ 42.024885] Waiting for root device /dev/mmcblk0...
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Krzysztof Kozlowski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/exynos4210.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index a9f8a5c8688..77fbe1baabc 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -405,7 +405,7 @@ static void exynos4210_realize(DeviceState *socdev, Error
**errp)
* public datasheet which is very similar (implementing
* MMC Specification Version 4.0 being the only difference noted)
*/
- dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
+ dev = qdev_create(NULL, TYPE_S3C_SDHCI);
qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
qdev_init_nofail(dev);
--
2.20.1
- [PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state, (continued)
- [PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 26/41] target/arm: Rebuild hflags at EL changes, Peter Maydell, 2019/10/22
- [PULL 27/41] target/arm: Rebuild hflags at MSR writes, Peter Maydell, 2019/10/22
- [PULL 28/41] target/arm: Rebuild hflags at CPSR writes, Peter Maydell, 2019/10/22
- [PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes, Peter Maydell, 2019/10/22
- [PULL 30/41] target/arm: Rebuild hflags for M-profile, Peter Maydell, 2019/10/22
- [PULL 31/41] target/arm: Rebuild hflags for M-profile NVIC, Peter Maydell, 2019/10/22
- [PULL 32/41] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state, Peter Maydell, 2019/10/22
- [PULL 33/41] hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions, Peter Maydell, 2019/10/22
- [PULL 34/41] hw/sd/sdhci: Add dummy Samsung SDHCI controller, Peter Maydell, 2019/10/22
- [PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller,
Peter Maydell <=
- [PULL 36/41] hw/arm/xilinx_zynq: Use the IEC binary prefix definitions, Peter Maydell, 2019/10/22
- [PULL 37/41] hw/arm/mps2: Use the IEC binary prefix definitions, Peter Maydell, 2019/10/22
- [PULL 38/41] hw/arm/collie: Create the RAM in the board, Peter Maydell, 2019/10/22
- [PULL 39/41] hw/arm/omap2: Create the RAM in the board, Peter Maydell, 2019/10/22
- [PULL 41/41] hw/arm/digic4: Inline digic4_board_setup_ram() function, Peter Maydell, 2019/10/22
- [PULL 40/41] hw/arm/omap1: Create the RAM in the board, Peter Maydell, 2019/10/22