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[PULL 5/7] target/arm: Do not reject rt == rt2 for strexd
From: |
Peter Maydell |
Subject: |
[PULL 5/7] target/arm: Do not reject rt == rt2 for strexd |
Date: |
Tue, 19 Nov 2019 13:31:43 +0000 |
From: Richard Henderson <address@hidden>
There was too much cut and paste between ldrexd and strexd,
as ldrexd does prohibit two output registers the same.
Fixes: af288228995
Reported-by: Michael Goffioul <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Robert Foley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2ea9da7637b..b285b23858e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8934,7 +8934,7 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp
mop, bool rel)
|| (s->thumb && (a->rd == 13 || a->rt == 13))
|| (mop == MO_64
&& (a->rt2 == 15
- || a->rd == a->rt2 || a->rt == a->rt2
+ || a->rd == a->rt2
|| (s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;
--
2.20.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19
- [PULL 1/7] pl031: Expose RTCICR as proper WC register, Peter Maydell, 2019/11/19
- [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status, Peter Maydell, 2019/11/19
- [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes, Peter Maydell, 2019/11/19
- [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller, Peter Maydell, 2019/11/19
- [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd,
Peter Maydell <=
- [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0, Peter Maydell, 2019/11/19
- [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY, Peter Maydell, 2019/11/19
- Re: [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19